a2o/dev/sim/coco
Bill Flynn 9b06ab5cc7
Update readme.md
..
build_st init
build_sweetpea add dev
A2L2.py nclk changes
A2O.py nclk changes
Makefile.litex nclk changes
Makefile.node nclk changes
Makefile.smt nclk changes
Makefile.st nclk changes
Makefile.sweetpea add dev
Makefile.verilator add dev
Makefile.wb nclk changes
OPEnv.py nclk changes
boot.lst add dev
cocotb_icarus.v nclk changes
cocotb_icarus_node.v nclk changes
cocotb_litex.v nclk changes
makegtkw add dev
pyvcd.gtkw add dev
readme.md Update readme.md
results.xml init
sim.png add dev
sim.txt litex
tb.py nclk changes
tb_node.py nclk changes
verilog add dev
wtf.gtkw random tst, bios

readme.md

Cocotb Sim Experiments

Core-only version with partial implementation of Python A2L2 interface

  • testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac

Core+wrapper version with partial implementation of A2Node (direct memory)

  • testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac

Core+wrapper version with implementation of A2Node (Wishbone system bus)

  • testbench provides 4B Wishbone memory interface (using cocoext-wishbone for now)
make -f Makefile.wb build |& grep -v Anac