9b06ab5cc7 | 2 years ago | |
---|---|---|
.. | ||
build_st | 3 years ago | |
build_sweetpea | 3 years ago | |
A2L2.py | 2 years ago | |
A2O.py | 2 years ago | |
Makefile.litex | 2 years ago | |
Makefile.node | 2 years ago | |
Makefile.smt | 2 years ago | |
Makefile.st | 2 years ago | |
Makefile.sweetpea | 3 years ago | |
Makefile.verilator | 3 years ago | |
Makefile.wb | 2 years ago | |
OPEnv.py | 2 years ago | |
boot.lst | 3 years ago | |
cocotb_icarus.v | 2 years ago | |
cocotb_icarus_node.v | 2 years ago | |
cocotb_litex.v | 2 years ago | |
makegtkw | 3 years ago | |
pyvcd.gtkw | 3 years ago | |
readme.md | 2 years ago | |
results.xml | 3 years ago | |
sim.png | 3 years ago | |
sim.txt | 2 years ago | |
tb.py | 2 years ago | |
tb_node.py | 2 years ago | |
verilog | 3 years ago | |
wtf.gtkw | 2 years ago |
readme.md
Cocotb Sim Experiments
Core-only version with partial implementation of Python A2L2 interface
- testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac
Core+wrapper version with partial implementation of A2Node (direct memory)
- testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac
Core+wrapper version with implementation of A2Node (Wishbone system bus)
- testbench provides 4B Wishbone memory interface (using cocoext-wishbone for now)
make -f Makefile.wb build |& grep -v Anac