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@ -23,7 +23,6 @@ from A2L2 import *
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async def init(dut, sim):
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"""Initialize inputs. """
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dut.nclk.value = 0
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dut.scan_in.value = 0
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dut.an_ac_reset_1_complete.value = 0
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dut.an_ac_reset_2_complete.value = 0
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@ -64,9 +63,8 @@ async def init(dut, sim):
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async def config(dut, sim):
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"""Configure node, etc. """
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await RisingEdge(dut.clk_1x)
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await RisingEdge(sim.sigClk)
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# trilib/tri.vh:`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5xClk
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async def genReset(dut, sim):
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"""Generate reset. """
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@ -74,35 +72,35 @@ async def genReset(dut, sim):
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done = False
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while not done:
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await RisingEdge(dut.clk_1x)
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await RisingEdge(sim.sigClk)
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if sim.cycle < sim.resetCycle:
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if first:
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dut._log.info(f'[{sim.cycle:08d}] Resetting...')
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first = False
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dut.nclk[1].value = 1
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sim.sigRst.value = 1
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elif not done:
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dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
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dut.nclk[1].value = 0
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sim.sigRst.value = 0
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done = True
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sim.resetDone = True
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async def genClocks(dut, sim):
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"""Generate 1x, 2x, 4x clock pulses, depending on parms. """
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if sim.clk2x and sim.clk4x:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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if sim.sigClk2x is not None and sim.sigClk4x is not None:
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sim.clk1x = Clock(sim.sigClk, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
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sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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sim.clk4x = Clock(dut.nclk[3], 2, 'ns')
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sim.clk4x = Clock(sim.sigClk4x, 2, 'ns')
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await cocotb.start(sim.clk4x.start())
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elif sim.clk2x:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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elif sim.sigClk2x is not None:
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sim.clk1x = Clock(sim.sigClk, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
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sim.clk2x = Clock(sim.sigClk2x, 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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else:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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sim.clk1x = Clock(sim.sigClk, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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@ -113,7 +111,7 @@ async def genClocks(dut, sim):
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if cycle % sim.hbCycles == 0:
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dut._log.info(f'[{cycle:08d}] ...tick...')
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await RisingEdge(dut.clk_1x)
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await RisingEdge(sim.sigClk)
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dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
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sim.ok = False
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@ -128,7 +126,7 @@ async def memory(dut, sim):
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sim.msg(f'{me}: started.')
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while ok:
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await RisingEdge(dut.clk_1x)
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await RisingEdge(sim.sigClk)
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try:
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addr = dut.mem_adr.value.integer
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@ -168,7 +166,7 @@ async def checker(dut, sim):
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while ok:
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await RisingEdge(dut.clk_1x)
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await RisingEdge(sim.sigClk)
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if not sim.resetDone:
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continue
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@ -200,6 +198,9 @@ async def tb_node(dut):
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sim = Sim(dut)
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sim.mem = Memory(sim)
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sim.maxCycles = 20000
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sim.sigClk = dut.clk
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sim.sigRst = dut.rst
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sim.resetAddr = 0xFFFFFFFC
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'''
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# rom
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@ -240,6 +241,13 @@ async def tb_node(dut):
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}
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]
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
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@ -257,13 +265,6 @@ async def tb_node(dut):
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# start interfaces
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await cocotb.start(scom(dut, sim))
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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await cocotb.start(A2O.driver(dut, sim))
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await cocotb.start(memory(dut, sim))
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@ -272,14 +273,15 @@ async def tb_node(dut):
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await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))
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await Timer((sim.resetCycle + 5)*8, units='ns')
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if dut.nclk[1].value != 0:
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if sim.sigRst.value != 0:
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sim.ok = False
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sim.fail = 'Reset active too long!'
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# config stuff
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# config'd in tri_a2o.vh
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# config for a2onode w/1 req buffer
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# a2node_verilotor defines have these set already
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#sim.a2o.config.creditsLd = 1
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#sim.a2o.config.creditsSt = 1
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#sim.a2o.config.creditsLdStSingle = True
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@ -296,7 +298,7 @@ async def tb_node(dut):
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# release thread(s)
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dut.an_ac_pm_thread_stop.value = 0
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await RisingEdge(dut.clk_1x)
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await RisingEdge(sim.sigClk)
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dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
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# should await sim.done
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@ -317,6 +319,8 @@ async def tb_node_wb(dut):
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sim = Sim(dut)
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sim.mem = Memory(sim)
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sim.maxCycles = 20000
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sim.sigClk = dut.clk
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sim.sigRst = dut.rst
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# rom+bios+arcitst
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sim.memFiles = [
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@ -326,6 +330,13 @@ async def tb_node_wb(dut):
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}
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]
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
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@ -337,23 +348,14 @@ async def tb_node_wb(dut):
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await init(dut, sim)
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# start clocks,reset
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await cocotb.start(genClocksLitex(dut, sim))
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await cocotb.start(genResetLitex(dut, sim))
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await cocotb.start(genClocks(dut, sim))
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await cocotb.start(genReset(dut, sim))
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# start interfaces
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await cocotb.start(scom(dut, sim))
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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await cocotb.start(A2O.driver(dut, sim))
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# sim memory
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#await cocotb.start(memory(dut, sim))
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# wishbone memory
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from cocotbext.wishbone.monitor import WishboneSlave
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# slave should take non-iterator for datgen and call it with f(self.bus) if next(f) fails
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@ -367,7 +369,7 @@ async def tb_node_wb(dut):
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"datrd": "wb_datr"
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}
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a2l2Iterable = A2L2Iterable()
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wbs = WishboneSlave(dut, None, dut.clk_1x, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
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wbs = WishboneSlave(dut, None, sim.sigClk, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
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A2L2.addWBSlave(dut, sim, wbSignals)
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wbs.add_callback(A2L2.wbSlave)
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@ -376,21 +378,10 @@ async def tb_node_wb(dut):
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await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))
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await Timer((sim.resetCycle + 5)*8, units='ns')
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if dut.nclk[1].value != 0:
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if sim.sigRst.value != 0:
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sim.ok = False
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sim.fail = 'Reset active too long!'
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# config stuff
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# config for a2onode w/1 req buffer
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# a2node_verilator defines have these set already
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#sim.a2o.config.creditsLd = 1
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#sim.a2o.config.creditsSt = 1
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#sim.a2o.config.creditsLdStSingle = True
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# original fpga design needed 4 cred, no fwd (set in logic currently)
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#sim.a2o.lsDataForward = 0 # disable=1
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await A2O.config(dut, sim)
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await cocotb.start(A2O.checker(dut, sim))
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@ -400,7 +391,7 @@ async def tb_node_wb(dut):
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# release thread(s)
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dut.an_ac_pm_thread_stop.value = 0
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await RisingEdge(dut.clk_1x)
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await RisingEdge(sim.sigClk)
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dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
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# should await sim.done
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@ -414,60 +405,16 @@ async def tb_node_wb(dut):
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assert False
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# ************************************************************************************************
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# make these generic someday (sigs could be in sim, or passed in)
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async def genResetLitex(dut, sim):
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"""Generate reset. """
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first = True
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done = False
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while not done:
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await RisingEdge(dut.clk_1x)
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if sim.cycle < sim.resetCycle:
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if first:
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dut._log.info(f'[{sim.cycle:08d}] Resetting...')
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first = False
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dut.rst.value = 1
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elif not done:
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dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
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dut.rst.value = 0
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done = True
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sim.resetDone = True
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async def genClocksLitex(dut, sim):
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"""Generate 1x, 2x clock pulses, depending on parms. """
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if sim.clk2x:
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sim.clk1x = Clock(dut.clk_1x, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(dut.clk_2x, 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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else:
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sim.clk1x = Clock(dut.clk_1x, 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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for cycle in range(sim.maxCycles):
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sim.cycle = cycle
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if cycle % sim.hbCycles == 0:
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dut._log.info(f'[{cycle:08d}] ...tick...')
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await RisingEdge(dut.clk_1x)
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dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
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sim.ok = False
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sim.fail = 'Max cycle reached.'
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@cocotb.test()
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async def tb_litex(dut):
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"""A2O wit litex interface"""
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"""A2O with litex interface"""
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sim = Sim(dut)
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sim.mem = Memory(sim)
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sim.maxCycles = 20000
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sim.resetAddr = None # set to 00000000 in rtl define
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sim.sigClk = dut.clk
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sim.sigRst = dut.rst
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# rom+bios+arcitst
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sim.memFiles = [
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@ -477,6 +424,17 @@ async def tb_litex(dut):
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}
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]
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sim.config.a2l2 = DotMap({
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'badAddr': [('E0','E0', 'IRW')]
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})
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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for i in range(len(sim.memFiles)):
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
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@ -492,23 +450,14 @@ async def tb_litex(dut):
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dut.cfg_wr.value = 0
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# start clocks,reset
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await cocotb.start(genClocksLitex(dut, sim))
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await cocotb.start(genResetLitex(dut, sim))
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await cocotb.start(genClocks(dut, sim))
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await cocotb.start(genReset(dut, sim))
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# start interfaces
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await cocotb.start(scom(dut, sim))
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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await cocotb.start(A2O.driver(dut, sim))
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# sim memory
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#await cocotb.start(memory(dut, sim))
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# wishbone memory
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from cocotbext.wishbone.monitor import WishboneSlave
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# slave should take non-iterator for datgen and call it with f(self.bus) if next(f) fails
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@ -522,7 +471,7 @@ async def tb_litex(dut):
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"datrd": "wb_datr"
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}
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a2l2Iterable = A2L2Iterable()
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wbs = WishboneSlave(dut, None, dut.clk_1x, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
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wbs = WishboneSlave(dut, None, sim.sigClk, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
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A2L2.addWBSlave(dut, sim, wbSignals)
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wbs.add_callback(A2L2.wbSlave)
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@ -537,15 +486,6 @@ async def tb_litex(dut):
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# config stuff
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# config for a2onode w/1 req buffer
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# a2node_verilator defines have these set already
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#sim.a2o.config.creditsLd = 1
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#sim.a2o.config.creditsSt = 1
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#sim.a2o.config.creditsLdStSingle = True
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# original fpga design needed 4 cred, no fwd (set in logic currently)
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#sim.a2o.lsDataForward = 0 # disable=1
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await A2O.config(dut, sim)
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await cocotb.start(A2O.checker(dut, sim))
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openpowerwtf
3 years ago