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9cca046fa4
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2 years ago | |
|---|---|---|
| .. | ||
| build_smt2 | ||
| build_st | ||
| build_sweetpea | ||
| A2L2.py | ||
| A2O.py | 2 years ago | |
| Makefile.litex | ||
| Makefile.node | ||
| Makefile.smt2 | ||
| Makefile.st | ||
| Makefile.sweetpea | ||
| Makefile.verilator | ||
| Makefile.wb | ||
| OPEnv.py | ||
| boot.lst | ||
| cocotb_icarus.v | ||
| cocotb_icarus_node.v | ||
| cocotb_litex.v | 2 years ago | |
| makegtkw | ||
| pyvcd.gtkw | ||
| readme.md | ||
| results.xml | ||
| sim.png | ||
| sim.txt | 2 years ago | |
| tb.py | ||
| tb_node.py | 2 years ago | |
| verilog | ||
| wtf.gtkw | ||
readme.md
Cocotb Sim Experiments
Core-only version with partial implementation of Python A2L2 interface
- testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac
Core+wrapper version with partial implementation of A2Node (direct memory)
- testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac
Core+wrapper version with implementation of A2Node (Wishbone system bus)
- testbench provides 4B Wishbone memory interface (using cocoext-wishbone for now)
make -f Makefile.wb build |& grep -v Anac
``
* update wrapper to include normal Litex, etc. I/O (WB plus ints, config, etc.)
* add Litex core definition (migen)
* can add L2 mem
* can add multiple core intefaces (SMP)
* can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)