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# RTL
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## fpga/sim arrays
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* arrays that had 2x/4x clks
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```
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trilib/tri_144x78_2r4w.v
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trilib/tri_64x72_1r1w.v
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trilib/tri_cam_16x143_1r1w1c.v
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trilib/tri_cam_32x143_1r1w1c.v
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# these two should be checked with cycle counts, etc. vs originals - might not cause errors if wrong...
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# at least one matches!
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# BHT...test3: orig= [00014100] Passing IAR detected: 000007F0 new= [00014100] Passing IAR detected: 000007F0
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# LRU won't be checked until doing TLB translates, and that logic will be rewritten for radix before that
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trilib/tri_512x16_1r1w_1.v
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trilib/tri_128x16_1r1w_1.v
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```
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* also got rid of reset_q usages (clk and reset in same nclk vector)
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***i doubt reset is needed in any of the array components***
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```
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trilib/tri_128x16_1r1w_1.v: reg reset_q;
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trilib/tri_512x16_1r1w_1.v: reg reset_q;
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trilib/tri_64x72_1r1w.v: reg reset_q;
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trilib/tri_cam_16x143_1r1w1c.v: reg sreset_q;
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trilib/tri_cam_32x143_1r1w1c.v: reg sreset_q;
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trilib/tri_iuq_cpl_arr.v: reg reset_q;
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```
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### arrays using clk4x
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* 4W was done with clk4x
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* should be built for fpga with 4 arrays and a 'valid' array pointing to last write per entry
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```
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grep "nclk\[3\]" trilib/*
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trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x
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```
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### arrays using clk2x
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```
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grep "nclk\[2\]" trilib/*
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trilib/tri_128x16_1r1w_1.v: assign clk2x = nclk[2];
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trilib/tri_128x16_1r1w_1.v: always @(posedge nclk[2])
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trilib/tri_144x78_2r4w.v: assign wr_mux_ctrl = {nclk[0], nclk[2]};
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trilib/tri_512x16_1r1w_1.v: assign clk2x = nclk[2];
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trilib/tri_64x72_1r1w.v: assign clk2x = nclk[2];
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trilib/tri_cam_16x143_1r1w1c.v: assign clk2x = nclk[2];
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trilib/tri_cam_16x143_1r1w1c.v: always @(posedge nclk[2])
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trilib/tri_cam_32x143_1r1w1c.v: assign clk2x = nclk[2];
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trilib/tri_cam_32x143_1r1w1c.v: always @(posedge nclk[2])
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```
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* IERAT, DERAT (cams)
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* BTB, SPR (1R,1W,read-before-write??)
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```
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grep tri_64x72 work/*
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work/iuq_btb.v: tri_64x72_1r1w btb0(
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work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr(
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```
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* BHT (bitwrite)
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```
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grep tri_512x16_1r1w_1 trilib/*
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trilib/tri_512x16_1r1w_1.v:module tri_512x16_1r1w_1(
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trilib/tri_bht_1024x8_1r1w.v: tri_512x16_1r1w_1 bht0(
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trilib/tri_bht_512x4_1r1w.v: tri_512x16_1r1w_1 bht0(
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```
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* MMU LRU (bitwrite)
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```
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grep tri_128x16_1r1w_1 work/*
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work/mmq.v: //tri.tri_128x16_1r1w_1 #(.`EXPAND_TYPE(`EXPAND_TYPE)) lru_array0(
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work/mmq.v: tri_128x16_1r1w_1 lru_array0(
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```
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