issues 13,14: single clk, no more nclk
openpowerwtf
1 year ago
parent
24d56dc84b
commit
af556071b0
@ -1,427 +0,0 @@
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#!/usr/bin/python3
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#
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# Parse table comments and create equations.
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from optparse import OptionParser
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import re
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from shutil import copyfile
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#--------------------------------------------------------------------------------------------------
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# Initialize
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TYPE_INPUT = 0
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TYPE_OUTPUT = 1
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TYPE_SKIP = 99
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lines = []
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tableMatches = []
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tableNames = []
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tableLines = []
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tables = {}
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failOnError = True
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inFile = 'test.vhdl'
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outFileExt = 'vtable'
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overwrite = True
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backupExt = 'orig'
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backup = True
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noisy = False
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quiet = False
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verilog = False
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#--------------------------------------------------------------------------------------------------
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# Handle command line
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usage = 'vtable [options] inFile'
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parser = OptionParser(usage)
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parser.add_option('-f', '--outfile', dest='outFile', help='output file, default=[inFile]' + outFileExt)
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parser.add_option('-o', '--overwrite', dest='overwrite', help='overwrite inFile, default=' + str(overwrite))
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parser.add_option('-b', '--backup', dest='backup', help='backup original file, default=' + str(backup))
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parser.add_option('-q', '--quiet', dest='quiet', action='store_true', help='quiet messages, default=' + str(quiet))
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parser.add_option('-n', '--noisy', dest='noisy', action='store_true', help='noisy messages, default=' + str(noisy))
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parser.add_option('-V', '--verilog', dest='verilog', action='store_true', help='source is verilog, default=' + str(verilog))
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options, args = parser.parse_args()
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if len(args) != 1:
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parser.error(usage)
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quit(-1)
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else:
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inFile = args[0]
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if options.overwrite == '0':
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overwrite = False
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elif options.overwrite == '1':
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overwrite == True
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if options.outFile is not None:
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parser.error('Can\'t specify outfile and overrite!')
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quit(-1)
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elif options.overwrite is not None:
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parser.error('overwrite: 0|1')
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quit(-1)
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if options.quiet is not None:
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quiet = True
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if options.noisy is not None:
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noisy = True
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if options.verilog is not None:
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verilog = True
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if options.backup == '0':
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backup = False
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elif options.backup == '1':
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backup == True
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elif options.backup is not None:
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parser.error('backup: 0|1')
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quit(-1)
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if options.outFile is not None:
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outFile = options.outFile
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elif overwrite:
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outFile = inFile
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else:
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outFile = inFile + '.' + outFileExt
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backupFile = inFile + '.' + backupExt
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#--------------------------------------------------------------------------------------------------
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# Objects
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class Signal:
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def __init__(self, name, type):
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self.name = name;
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self.type = type;
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class Table:
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def __init__(self, name):
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self.name = name
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self.source = []
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self.signals = {}
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self.signalsByCol = {}
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self.typesByCol = {}
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self.specs = [] # list of specsByCol
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self.equations = []
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self.added = False
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def validate(self):
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# check that all signals have a good type
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for col in self.signalsByCol:
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if col not in self.typesByCol:
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error('Table ' + self.name + ': no signal type for ' + self.signalsByCol[col])
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elif self.typesByCol[col] == None:
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error('Table ' + self.name + ': bad signal type (' + str(self.typesByCol[col]) + ') for ' + str(self.signalsByCol[col]))
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def makeRTL(self, form=None):
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outputsByCol = {}
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#for col,type in self.typesByCol.items():
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for col in sorted(self.typesByCol):
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type = self.typesByCol[col]
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if type == TYPE_OUTPUT:
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if col in self.signalsByCol:
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outputsByCol[col] = self.signalsByCol[col]
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else:
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print(self.signalsByCol)
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print(self.typesByCol)
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error('Table ' + self.name + ': output is specified in col ' + str(col) + ' but no signal exists')
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#for sigCol,sig in outputsByCol.items():
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for sigCol in sorted(outputsByCol):
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sig = outputsByCol[sigCol]
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if not verilog:
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line = sig + ' <= '
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else:
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line = 'assign ' + sig + ' = '
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nonzero = False
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for specsByCol in self.specs:
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terms = []
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if sigCol not in specsByCol:
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#error('* Output ' + sig + ' has no specified value for column ' + str(col))
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1 # no error, can be dontcare
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elif specsByCol[sigCol] == '1':
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for col,val in specsByCol.items():
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if col not in self.typesByCol:
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if noisy:
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error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ') - no associated signal', False) #wtf UNTIL CAN HANDLE COMMENTS AT END!!!!!!!!!!!!!!!!!!!
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elif self.typesByCol[col] == TYPE_INPUT:
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if val == '0':
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terms.append(opNot + self.signalsByCol[col])
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if nonzero and len(terms) == 1:
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line = line + ') ' + opOr + '\n (';
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elif len(terms) == 1:
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line = line + '\n ('
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nonzero = True
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elif val == '1':
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terms.append(self.signalsByCol[col])
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if nonzero and len(terms) == 1:
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line = line + ') ' + opOr + '\n (';
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elif len(terms) == 1:
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line = line + '\n ('
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nonzero = True
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else:
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error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ')')
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if len(terms) > 0:
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line = line + (' ' + opAnd + ' ').join(terms)
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if not nonzero:
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line = line + zero + ";";
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else:
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line = line + ');'
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self.equations.append(line)
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return self.equations
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def printv(self):
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self.makeRTL()
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print('\n'.join(self.equations))
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def printinfo(self):
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print('Table: ' + self.name)
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print
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for l in self.source:
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print(l)
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print
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print('Signals by column:')
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for col in sorted(self.signalsByCol):
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print('{0:>3}. {1:} ({2:}) '.format(col, self.signalsByCol[col], 'in' if self.typesByCol[col] == TYPE_INPUT else 'out'))
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#--------------------------------------------------------------------------------------------------
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# Functions
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def error(msg, quitOverride=None):
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print('*** ' + msg)
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if quitOverride == False:
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1
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elif (quitOverride == None) or failOnError:
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quit(-10)
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elif quitOverride:
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quit(-10)
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#--------------------------------------------------------------------------------------------------
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# Do something
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if not verilog:
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openBracket = '('
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closeBracket = ')'
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opAnd = 'and'
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opOr = 'or'
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opNot = 'not '
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zero = "'0'"
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tablePattern = re.compile(r'^\s*?--tbl(?:\s+([^\s]+).*$|\s*$)')
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tableGenPattern = re.compile(r'^\s*?--vtable(?:\s+([^\s]+).*$)')
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commentPattern = re.compile(r'^\s*?(--.*$|\s*$)')
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tableLinePattern = re.compile(r'^.*?--(.*)')
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namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')
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else:
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openBracket = '['
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closeBracket = ']'
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opAnd = '&'
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opOr = '|'
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opNot = '~'
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zero = "'b0"
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tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)')
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tableGenPattern = re.compile(r'^\s*?\/\/vtable(?:\s+([^\s]+).*$)')
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commentPattern = re.compile(r'^\s*?(\/\/.*$|\s*$)')
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tableLinePattern = re.compile(r'^.*?\/\/(.*)')
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namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')
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# find the lines with table spec
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try:
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inf = open(inFile)
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for i, line in enumerate(inf):
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lines.append(line.strip('\n'))
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for match in re.finditer(tablePattern, line):
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tableMatches.append(i)
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inf.close()
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except Exception as e:
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error('Error opening input file ' + inFile + '\n' + str(e), True)
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# validate matches; should be paired, nothing but comments and empties; table may be named
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# between them
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for i in range(0, len(tableMatches), 2):
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if i + 1 > len(tableMatches) - 1:
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error('Mismatched table tags.\nFound so far: ' + ', '.join(tableNames), True)
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tLines = lines[tableMatches[i]:tableMatches[i+1]+1]
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tableLines.append(tLines)
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tName = re.match(tablePattern, lines[tableMatches[i]]).groups()[0]
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if tName is None:
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tName = 'noname_' + str(tableMatches[i] + 1)
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tableNames.append(tName)
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for line in tLines:
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if not re.match(commentPattern, line):
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error('Found noncomment, nonempty line in table ' + tName + ':\n' + line, True)
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print('Found tables: ' + ', '.join(tableNames))
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# build table objects
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for table, tName in zip(tableLines, tableNames):
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print('Parsing ' + tName + '...')
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namesByCol = {}
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colsByName = {}
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bitsByCol = {}
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typesByCol = {}
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specs = []
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# parse the table - do by Table.parse()
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tLines = table[1:-1] # exclude --tbl
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for line in tLines:
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if line.strip() == '':
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continue
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try:
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spec = re.search(tableLinePattern, line).groups()[0]
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except Exception as e:
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error('Problem parsing table line:\n' + line, True)
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if len(spec) > 0:
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if spec[0] == 'n':
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for match in re.finditer(namePattern, spec[1:]):
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# col 0 is first col after n
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namesByCol[match.start()] = match.groups()[0]
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colsByName[match.groups()[0]] = match.start()
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elif spec[0] == 'b':
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for i, c in enumerate(spec[1:]):
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if c == ' ' or c == '|':
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continue
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try:
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bit = int(c)
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except:
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error('Unexpected char in bit line at position ' + str(i) + ' (' + c + ')\n' + line)
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bit = None
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if i in bitsByCol and bitsByCol[i] is not None:
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bitsByCol[i] = bitsByCol[i]*10+bit
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else:
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bitsByCol[i] = bit
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elif spec[0] == 't':
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for i, c in enumerate(spec[1:]):
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if c.lower() == 'i':
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typesByCol[i] = TYPE_INPUT
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elif c.lower() == 'o':
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typesByCol[i] = TYPE_OUTPUT
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elif c.lower() == '*':
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typesByCol[i] = TYPE_SKIP
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elif c != ' ':
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error('Unexpected char in type line at position ' + str(i) + ' (' + c + ')\n' + line)
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typesByCol[i] = None
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else:
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typesByCol[i] = None
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elif spec[0] == 's':
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specsByCol = {}
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for i, c in enumerate(spec[1:]):
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if c == '0' or c == '1':
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specsByCol[i] = c
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specs.append(specsByCol)
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else:
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#print('other:')
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#print(line)
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1
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# create table object
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# add strand to name where defined; don't combine for now into vector
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# consecutive strands belong to the last defined name
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lastName = None
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lastCol = 0
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signalsByCol = {}
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for col,name in namesByCol.items(): # load with unstranded names
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signalsByCol[col] = name
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# sort by col so consecutive columns can be easily tracked
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#for col,val in bitsByCol.items(): # update with stranded names
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for col in sorted(bitsByCol):
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val = bitsByCol[col]
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if col > lastCol + 1:
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lastName = None
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if val is None:
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lastName = None
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if col in namesByCol:
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if val is None:
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signalsByCol[col] = namesByCol[col]
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else:
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lastName = namesByCol[col]
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signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
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elif lastName is not None:
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signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
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else:
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error('Can\'t associate bit number ' + str(val) + ' in column ' + str(col) + ' with a signal name.')
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lastCol = col
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t = Table(tName)
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t.source = table
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t.signalsByCol = signalsByCol
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t.typesByCol = typesByCol
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t.specs = specs
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tables[tName] = t
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for name in tables:
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t = tables[name]
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t.validate()
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t.makeRTL()
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print()
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print('Results:')
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# find the lines with generate spec and replace them with new version
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outLines = []
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inTable = False
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for i, line in enumerate(lines):
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if not inTable:
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match = re.search(tableGenPattern, line)
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if match is not None:
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tName = match.groups(1)[0]
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if tName not in tables:
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if tName == 1:
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tName = '<blank>'
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error('Found vtable start for \'' + tName + '\' but didn\'t generate that table: line ' + str(i+1) + '\n' + line, True)
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else:
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outLines.append(line)
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outLines += tables[tName].equations
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tables[tName].added = True
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inTable = True
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else:
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outLines.append(line)
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else:
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match = re.search(tableGenPattern, line)
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if match is not None:
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if match.groups(1)[0] != tName:
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error('Found vtable end for \'' + match.groups(1)[0] + '\' but started table \'' + tName + '\': line ' + str(i+1) + '\n' + line, True)
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outLines.append(line)
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inTable = False
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else:
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1#print('stripped: ' + line)
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if backup:
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try:
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copyfile(inFile, backupFile)
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except Exception as e:
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error('Error creating backup file!\n' + str(e), True)
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try:
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of = open(outFile, 'w')
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for line in outLines:
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of.write("%s\n" % line)
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except Exception as e:
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error('Error writing output file ' + outFile + '!\n' + str(e), True)
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print('Generated ' + str(len(tables)) + ' tables: ' + ', '.join(tableNames))
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notAdded = {}
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for table in tables:
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if not tables[table].added:
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notAdded[table] = True
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print('Output file: ' + outFile)
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if backup:
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print('Backup file: ' + backupFile)
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if len(notAdded) != 0:
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error('Tables generated but not added to file! ' + ', '.join(notAdded))
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff