issues 13,14: single clk, no more nclk
openpowerwtf
3 years ago
parent
24d56dc84b
commit
af556071b0
@ -1,427 +0,0 @@
|
||||
#!/usr/bin/python3
|
||||
#
|
||||
# Parse table comments and create equations.
|
||||
|
||||
from optparse import OptionParser
|
||||
import re
|
||||
from shutil import copyfile
|
||||
|
||||
#--------------------------------------------------------------------------------------------------
|
||||
# Initialize
|
||||
|
||||
TYPE_INPUT = 0
|
||||
TYPE_OUTPUT = 1
|
||||
TYPE_SKIP = 99
|
||||
|
||||
lines = []
|
||||
tableMatches = []
|
||||
tableNames = []
|
||||
tableLines = []
|
||||
tables = {}
|
||||
|
||||
failOnError = True
|
||||
inFile = 'test.vhdl'
|
||||
outFileExt = 'vtable'
|
||||
overwrite = True
|
||||
backupExt = 'orig'
|
||||
backup = True
|
||||
noisy = False
|
||||
quiet = False
|
||||
verilog = False
|
||||
|
||||
#--------------------------------------------------------------------------------------------------
|
||||
# Handle command line
|
||||
|
||||
usage = 'vtable [options] inFile'
|
||||
|
||||
parser = OptionParser(usage)
|
||||
parser.add_option('-f', '--outfile', dest='outFile', help='output file, default=[inFile]' + outFileExt)
|
||||
parser.add_option('-o', '--overwrite', dest='overwrite', help='overwrite inFile, default=' + str(overwrite))
|
||||
parser.add_option('-b', '--backup', dest='backup', help='backup original file, default=' + str(backup))
|
||||
parser.add_option('-q', '--quiet', dest='quiet', action='store_true', help='quiet messages, default=' + str(quiet))
|
||||
parser.add_option('-n', '--noisy', dest='noisy', action='store_true', help='noisy messages, default=' + str(noisy))
|
||||
parser.add_option('-V', '--verilog', dest='verilog', action='store_true', help='source is verilog, default=' + str(verilog))
|
||||
|
||||
options, args = parser.parse_args()
|
||||
|
||||
if len(args) != 1:
|
||||
parser.error(usage)
|
||||
quit(-1)
|
||||
else:
|
||||
inFile = args[0]
|
||||
|
||||
if options.overwrite == '0':
|
||||
overwrite = False
|
||||
elif options.overwrite == '1':
|
||||
overwrite == True
|
||||
if options.outFile is not None:
|
||||
parser.error('Can\'t specify outfile and overrite!')
|
||||
quit(-1)
|
||||
elif options.overwrite is not None:
|
||||
parser.error('overwrite: 0|1')
|
||||
quit(-1)
|
||||
|
||||
if options.quiet is not None:
|
||||
quiet = True
|
||||
|
||||
if options.noisy is not None:
|
||||
noisy = True
|
||||
|
||||
if options.verilog is not None:
|
||||
verilog = True
|
||||
|
||||
if options.backup == '0':
|
||||
backup = False
|
||||
elif options.backup == '1':
|
||||
backup == True
|
||||
elif options.backup is not None:
|
||||
parser.error('backup: 0|1')
|
||||
quit(-1)
|
||||
|
||||
if options.outFile is not None:
|
||||
outFile = options.outFile
|
||||
elif overwrite:
|
||||
outFile = inFile
|
||||
else:
|
||||
outFile = inFile + '.' + outFileExt
|
||||
|
||||
backupFile = inFile + '.' + backupExt
|
||||
|
||||
#--------------------------------------------------------------------------------------------------
|
||||
# Objects
|
||||
|
||||
class Signal:
|
||||
|
||||
def __init__(self, name, type):
|
||||
self.name = name;
|
||||
self.type = type;
|
||||
|
||||
class Table:
|
||||
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.source = []
|
||||
self.signals = {}
|
||||
self.signalsByCol = {}
|
||||
self.typesByCol = {}
|
||||
self.specs = [] # list of specsByCol
|
||||
self.equations = []
|
||||
self.added = False
|
||||
|
||||
def validate(self):
|
||||
# check that all signals have a good type
|
||||
for col in self.signalsByCol:
|
||||
if col not in self.typesByCol:
|
||||
error('Table ' + self.name + ': no signal type for ' + self.signalsByCol[col])
|
||||
elif self.typesByCol[col] == None:
|
||||
error('Table ' + self.name + ': bad signal type (' + str(self.typesByCol[col]) + ') for ' + str(self.signalsByCol[col]))
|
||||
|
||||
def makeRTL(self, form=None):
|
||||
outputsByCol = {}
|
||||
|
||||
|
||||
#for col,type in self.typesByCol.items():
|
||||
for col in sorted(self.typesByCol):
|
||||
type = self.typesByCol[col]
|
||||
if type == TYPE_OUTPUT:
|
||||
if col in self.signalsByCol:
|
||||
outputsByCol[col] = self.signalsByCol[col]
|
||||
else:
|
||||
print(self.signalsByCol)
|
||||
print(self.typesByCol)
|
||||
error('Table ' + self.name + ': output is specified in col ' + str(col) + ' but no signal exists')
|
||||
|
||||
#for sigCol,sig in outputsByCol.items():
|
||||
for sigCol in sorted(outputsByCol):
|
||||
sig = outputsByCol[sigCol]
|
||||
if not verilog:
|
||||
line = sig + ' <= '
|
||||
else:
|
||||
line = 'assign ' + sig + ' = '
|
||||
nonzero = False
|
||||
for specsByCol in self.specs:
|
||||
terms = []
|
||||
if sigCol not in specsByCol:
|
||||
#error('* Output ' + sig + ' has no specified value for column ' + str(col))
|
||||
1 # no error, can be dontcare
|
||||
elif specsByCol[sigCol] == '1':
|
||||
for col,val in specsByCol.items():
|
||||
if col not in self.typesByCol:
|
||||
if noisy:
|
||||
error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ') - no associated signal', False) #wtf UNTIL CAN HANDLE COMMENTS AT END!!!!!!!!!!!!!!!!!!!
|
||||
elif self.typesByCol[col] == TYPE_INPUT:
|
||||
if val == '0':
|
||||
terms.append(opNot + self.signalsByCol[col])
|
||||
if nonzero and len(terms) == 1:
|
||||
line = line + ') ' + opOr + '\n (';
|
||||
elif len(terms) == 1:
|
||||
line = line + '\n ('
|
||||
nonzero = True
|
||||
elif val == '1':
|
||||
terms.append(self.signalsByCol[col])
|
||||
if nonzero and len(terms) == 1:
|
||||
line = line + ') ' + opOr + '\n (';
|
||||
elif len(terms) == 1:
|
||||
line = line + '\n ('
|
||||
nonzero = True
|
||||
else:
|
||||
error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ')')
|
||||
if len(terms) > 0:
|
||||
line = line + (' ' + opAnd + ' ').join(terms)
|
||||
if not nonzero:
|
||||
line = line + zero + ";";
|
||||
else:
|
||||
line = line + ');'
|
||||
self.equations.append(line)
|
||||
|
||||
return self.equations
|
||||
|
||||
def printv(self):
|
||||
self.makeRTL()
|
||||
print('\n'.join(self.equations))
|
||||
|
||||
def printinfo(self):
|
||||
print('Table: ' + self.name)
|
||||
print
|
||||
for l in self.source:
|
||||
print(l)
|
||||
print
|
||||
print('Signals by column:')
|
||||
for col in sorted(self.signalsByCol):
|
||||
print('{0:>3}. {1:} ({2:}) '.format(col, self.signalsByCol[col], 'in' if self.typesByCol[col] == TYPE_INPUT else 'out'))
|
||||
|
||||
|
||||
#--------------------------------------------------------------------------------------------------
|
||||
# Functions
|
||||
|
||||
def error(msg, quitOverride=None):
|
||||
print('*** ' + msg)
|
||||
if quitOverride == False:
|
||||
1
|
||||
elif (quitOverride == None) or failOnError:
|
||||
quit(-10)
|
||||
elif quitOverride:
|
||||
quit(-10)
|
||||
|
||||
#--------------------------------------------------------------------------------------------------
|
||||
# Do something
|
||||
|
||||
if not verilog:
|
||||
openBracket = '('
|
||||
closeBracket = ')'
|
||||
opAnd = 'and'
|
||||
opOr = 'or'
|
||||
opNot = 'not '
|
||||
zero = "'0'"
|
||||
tablePattern = re.compile(r'^\s*?--tbl(?:\s+([^\s]+).*$|\s*$)')
|
||||
tableGenPattern = re.compile(r'^\s*?--vtable(?:\s+([^\s]+).*$)')
|
||||
commentPattern = re.compile(r'^\s*?(--.*$|\s*$)')
|
||||
tableLinePattern = re.compile(r'^.*?--(.*)')
|
||||
namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')
|
||||
else:
|
||||
openBracket = '['
|
||||
closeBracket = ']'
|
||||
opAnd = '&'
|
||||
opOr = '|'
|
||||
opNot = '~'
|
||||
zero = "'b0"
|
||||
tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)')
|
||||
tableGenPattern = re.compile(r'^\s*?\/\/vtable(?:\s+([^\s]+).*$)')
|
||||
commentPattern = re.compile(r'^\s*?(\/\/.*$|\s*$)')
|
||||
tableLinePattern = re.compile(r'^.*?\/\/(.*)')
|
||||
namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')
|
||||
|
||||
# find the lines with table spec
|
||||
try:
|
||||
inf = open(inFile)
|
||||
for i, line in enumerate(inf):
|
||||
lines.append(line.strip('\n'))
|
||||
for match in re.finditer(tablePattern, line):
|
||||
tableMatches.append(i)
|
||||
inf.close()
|
||||
except Exception as e:
|
||||
error('Error opening input file ' + inFile + '\n' + str(e), True)
|
||||
|
||||
# validate matches; should be paired, nothing but comments and empties; table may be named
|
||||
# between them
|
||||
|
||||
for i in range(0, len(tableMatches), 2):
|
||||
|
||||
if i + 1 > len(tableMatches) - 1:
|
||||
error('Mismatched table tags.\nFound so far: ' + ', '.join(tableNames), True)
|
||||
|
||||
tLines = lines[tableMatches[i]:tableMatches[i+1]+1]
|
||||
tableLines.append(tLines)
|
||||
tName = re.match(tablePattern, lines[tableMatches[i]]).groups()[0]
|
||||
if tName is None:
|
||||
tName = 'noname_' + str(tableMatches[i] + 1)
|
||||
tableNames.append(tName)
|
||||
|
||||
for line in tLines:
|
||||
if not re.match(commentPattern, line):
|
||||
error('Found noncomment, nonempty line in table ' + tName + ':\n' + line, True)
|
||||
|
||||
print('Found tables: ' + ', '.join(tableNames))
|
||||
|
||||
# build table objects
|
||||
|
||||
for table, tName in zip(tableLines, tableNames):
|
||||
print('Parsing ' + tName + '...')
|
||||
namesByCol = {}
|
||||
colsByName = {}
|
||||
bitsByCol = {}
|
||||
typesByCol = {}
|
||||
specs = []
|
||||
|
||||
# parse the table - do by Table.parse()
|
||||
tLines = table[1:-1] # exclude --tbl
|
||||
for line in tLines:
|
||||
if line.strip() == '':
|
||||
continue
|
||||
try:
|
||||
spec = re.search(tableLinePattern, line).groups()[0]
|
||||
except Exception as e:
|
||||
error('Problem parsing table line:\n' + line, True)
|
||||
if len(spec) > 0:
|
||||
if spec[0] == 'n':
|
||||
for match in re.finditer(namePattern, spec[1:]):
|
||||
# col 0 is first col after n
|
||||
namesByCol[match.start()] = match.groups()[0]
|
||||
colsByName[match.groups()[0]] = match.start()
|
||||
elif spec[0] == 'b':
|
||||
for i, c in enumerate(spec[1:]):
|
||||
if c == ' ' or c == '|':
|
||||
continue
|
||||
try:
|
||||
bit = int(c)
|
||||
except:
|
||||
error('Unexpected char in bit line at position ' + str(i) + ' (' + c + ')\n' + line)
|
||||
bit = None
|
||||
if i in bitsByCol and bitsByCol[i] is not None:
|
||||
bitsByCol[i] = bitsByCol[i]*10+bit
|
||||
else:
|
||||
bitsByCol[i] = bit
|
||||
elif spec[0] == 't':
|
||||
for i, c in enumerate(spec[1:]):
|
||||
if c.lower() == 'i':
|
||||
typesByCol[i] = TYPE_INPUT
|
||||
elif c.lower() == 'o':
|
||||
typesByCol[i] = TYPE_OUTPUT
|
||||
elif c.lower() == '*':
|
||||
typesByCol[i] = TYPE_SKIP
|
||||
elif c != ' ':
|
||||
error('Unexpected char in type line at position ' + str(i) + ' (' + c + ')\n' + line)
|
||||
typesByCol[i] = None
|
||||
else:
|
||||
typesByCol[i] = None
|
||||
elif spec[0] == 's':
|
||||
specsByCol = {}
|
||||
for i, c in enumerate(spec[1:]):
|
||||
if c == '0' or c == '1':
|
||||
specsByCol[i] = c
|
||||
specs.append(specsByCol)
|
||||
else:
|
||||
#print('other:')
|
||||
#print(line)
|
||||
1
|
||||
|
||||
# create table object
|
||||
|
||||
# add strand to name where defined; don't combine for now into vector
|
||||
# consecutive strands belong to the last defined name
|
||||
lastName = None
|
||||
lastCol = 0
|
||||
signalsByCol = {}
|
||||
|
||||
for col,name in namesByCol.items(): # load with unstranded names
|
||||
signalsByCol[col] = name
|
||||
|
||||
# sort by col so consecutive columns can be easily tracked
|
||||
#for col,val in bitsByCol.items(): # update with stranded names
|
||||
for col in sorted(bitsByCol):
|
||||
val = bitsByCol[col]
|
||||
|
||||
if col > lastCol + 1:
|
||||
lastName = None
|
||||
if val is None:
|
||||
lastName = None
|
||||
if col in namesByCol:
|
||||
if val is None:
|
||||
signalsByCol[col] = namesByCol[col]
|
||||
else:
|
||||
lastName = namesByCol[col]
|
||||
signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
|
||||
elif lastName is not None:
|
||||
signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
|
||||
else:
|
||||
error('Can\'t associate bit number ' + str(val) + ' in column ' + str(col) + ' with a signal name.')
|
||||
lastCol = col
|
||||
|
||||
t = Table(tName)
|
||||
t.source = table
|
||||
t.signalsByCol = signalsByCol
|
||||
t.typesByCol = typesByCol
|
||||
t.specs = specs
|
||||
|
||||
tables[tName] = t
|
||||
|
||||
for name in tables:
|
||||
t = tables[name]
|
||||
t.validate()
|
||||
t.makeRTL()
|
||||
|
||||
print()
|
||||
print('Results:')
|
||||
|
||||
# find the lines with generate spec and replace them with new version
|
||||
outLines = []
|
||||
inTable = False
|
||||
for i, line in enumerate(lines):
|
||||
if not inTable:
|
||||
match = re.search(tableGenPattern, line)
|
||||
if match is not None:
|
||||
tName = match.groups(1)[0]
|
||||
if tName not in tables:
|
||||
if tName == 1:
|
||||
tName = '<blank>'
|
||||
error('Found vtable start for \'' + tName + '\' but didn\'t generate that table: line ' + str(i+1) + '\n' + line, True)
|
||||
else:
|
||||
outLines.append(line)
|
||||
outLines += tables[tName].equations
|
||||
tables[tName].added = True
|
||||
inTable = True
|
||||
else:
|
||||
outLines.append(line)
|
||||
else:
|
||||
match = re.search(tableGenPattern, line)
|
||||
if match is not None:
|
||||
if match.groups(1)[0] != tName:
|
||||
error('Found vtable end for \'' + match.groups(1)[0] + '\' but started table \'' + tName + '\': line ' + str(i+1) + '\n' + line, True)
|
||||
outLines.append(line)
|
||||
inTable = False
|
||||
else:
|
||||
1#print('stripped: ' + line)
|
||||
|
||||
if backup:
|
||||
try:
|
||||
copyfile(inFile, backupFile)
|
||||
except Exception as e:
|
||||
error('Error creating backup file!\n' + str(e), True)
|
||||
|
||||
try:
|
||||
of = open(outFile, 'w')
|
||||
for line in outLines:
|
||||
of.write("%s\n" % line)
|
||||
except Exception as e:
|
||||
error('Error writing output file ' + outFile + '!\n' + str(e), True)
|
||||
|
||||
print('Generated ' + str(len(tables)) + ' tables: ' + ', '.join(tableNames))
|
||||
notAdded = {}
|
||||
for table in tables:
|
||||
if not tables[table].added:
|
||||
notAdded[table] = True
|
||||
print('Output file: ' + outFile)
|
||||
if backup:
|
||||
print('Backup file: ' + backupFile)
|
||||
if len(notAdded) != 0:
|
||||
error('Tables generated but not added to file! ' + ', '.join(notAdded))
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,281 +0,0 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_128x16_1r1w_1(
|
||||
vdd,
|
||||
vcs,
|
||||
gnd,
|
||||
nclk,
|
||||
rd_act,
|
||||
wr_act,
|
||||
lcb_d_mode_dc,
|
||||
lcb_clkoff_dc_b,
|
||||
lcb_mpw1_dc_b,
|
||||
lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc,
|
||||
ccflush_dc,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
func_scan_in,
|
||||
func_scan_out,
|
||||
lcb_sg_0,
|
||||
lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0,
|
||||
lcb_abst_sl_thold_0,
|
||||
lcb_ary_nsl_thold_0,
|
||||
lcb_repr_sl_thold_0,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
bw,
|
||||
wr_adr,
|
||||
rd_adr,
|
||||
di,
|
||||
dout
|
||||
);
|
||||
parameter addressable_ports = 128; // number of addressable register in this array
|
||||
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
|
||||
parameter port_bitwidth = 16; // bitwidth of ports
|
||||
parameter ways = 1; // number of ways
|
||||
|
||||
// POWER PINS
|
||||
inout vdd;
|
||||
inout vcs;
|
||||
inout gnd;
|
||||
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
|
||||
input rd_act;
|
||||
input wr_act;
|
||||
|
||||
// DC TEST PINS
|
||||
input lcb_d_mode_dc;
|
||||
input lcb_clkoff_dc_b;
|
||||
input [0:4] lcb_mpw1_dc_b;
|
||||
input lcb_mpw2_dc_b;
|
||||
input [0:4] lcb_delay_lclkr_dc;
|
||||
|
||||
input ccflush_dc;
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input func_scan_in;
|
||||
output func_scan_out;
|
||||
|
||||
input lcb_sg_0;
|
||||
input lcb_sl_thold_0_b;
|
||||
input lcb_time_sl_thold_0;
|
||||
input lcb_abst_sl_thold_0;
|
||||
input lcb_ary_nsl_thold_0;
|
||||
input lcb_repr_sl_thold_0;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:6] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:6] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
input [0:15] bw;
|
||||
input [0:6] wr_adr;
|
||||
input [0:6] rd_adr;
|
||||
input [0:15] di;
|
||||
|
||||
output [0:15] dout;
|
||||
|
||||
// tri_128x16_1r1w_1
|
||||
|
||||
// Configuration Statement for NCsim
|
||||
//for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;
|
||||
|
||||
wire clk;
|
||||
wire [0:8] b0addra;
|
||||
wire [0:8] b0addrb;
|
||||
wire wea;
|
||||
wire web;
|
||||
wire wren_a;
|
||||
wire [0:15] w_data_in_0;
|
||||
wire [0:15] r_data_out_0_bram;
|
||||
|
||||
// Latches
|
||||
reg reset_q;
|
||||
reg [0:15] r_data_out_1_q;
|
||||
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:15] mem[0:127];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 128; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 128; j=j+1) begin: loc
|
||||
wire [0:15] dat;
|
||||
assign dat = mem[j][0:15];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign clk = nclk[0];
|
||||
|
||||
always @(posedge clk)
|
||||
begin: rlatch
|
||||
reset_q <= nclk[1];
|
||||
end
|
||||
|
||||
assign b0addra[2:8] = wr_adr;
|
||||
assign b0addrb[2:8] = rd_adr;
|
||||
|
||||
// Unused Address Bits
|
||||
assign b0addra[0:1] = 2'b00;
|
||||
assign b0addrb[0:1] = 2'b00;
|
||||
|
||||
// port a is a read-modify-write port
|
||||
assign wren_a = (bw != 0) & wr_act;
|
||||
assign wea = wren_a;
|
||||
assign web = 1'b0;
|
||||
assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
|
||||
assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
|
||||
assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
|
||||
assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
|
||||
assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
|
||||
assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
|
||||
assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
|
||||
assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
|
||||
assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
|
||||
assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
|
||||
assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
|
||||
assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
|
||||
assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
|
||||
assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
|
||||
assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
|
||||
assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r_data_out_1_q <= mem[b0addrb];
|
||||
if (wea) begin
|
||||
mem[b0addra] <= w_data_in_0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign r_data_out_0_bram = mem[b0addra];
|
||||
assign dout = r_data_out_1_q[0:15];
|
||||
|
||||
assign func_scan_out = func_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
|
||||
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
|
||||
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc, rd_act};
|
||||
endmodule
|
||||
@ -1,157 +0,0 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri-Lam Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_144x78_2r4w(
|
||||
// Inputs
|
||||
// Power
|
||||
inout vdd,
|
||||
inout gnd,
|
||||
// Clock & Scan
|
||||
input [0:`NCLK_WIDTH-1] nclk,
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// Pervasive
|
||||
//-------------------------------------------------------------------
|
||||
input delay_lclkr_dc,
|
||||
input mpw1_dc_b,
|
||||
input mpw2_dc_b,
|
||||
input func_sl_force,
|
||||
input func_sl_thold_0_b,
|
||||
input func_slp_sl_force,
|
||||
input func_slp_sl_thold_0_b,
|
||||
input sg_0,
|
||||
input scan_in,
|
||||
output scan_out,
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// Read Port
|
||||
//-------------------------------------------------------------------
|
||||
input r_late_en_1,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1,
|
||||
output [64-`GPR_WIDTH:77] r_data_out_1,
|
||||
input r_late_en_2,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2,
|
||||
output [64-`GPR_WIDTH:77] r_data_out_2,
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// Write Port
|
||||
//-------------------------------------------------------------------
|
||||
input w_late_en_1,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_1,
|
||||
input w_late_en_2,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_2,
|
||||
input w_late_en_3,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_3,
|
||||
input w_late_en_4,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_4
|
||||
);
|
||||
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [64-`GPR_WIDTH:77] mem[0:143];
|
||||
|
||||
reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
|
||||
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d;
|
||||
reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;
|
||||
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d;
|
||||
|
||||
reg [64-`GPR_WIDTH:77] r1d_q;
|
||||
wire [64-`GPR_WIDTH:77] r1d_d;
|
||||
reg [64-`GPR_WIDTH:77] r2d_q;
|
||||
wire [64-`GPR_WIDTH:77] r2d_d;
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 144; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 144; j=j+1) begin: loc
|
||||
wire [64-`GPR_WIDTH:63] dat;
|
||||
wire [0:7] par;
|
||||
// 4b0
|
||||
assign dat = mem[j][64-`GPR_WIDTH:63];
|
||||
assign par = mem[j][64:63 + `GPR_WIDTH/8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign r1a_d = r_addr_in_1;
|
||||
assign r2a_d = r_addr_in_2;
|
||||
|
||||
always @(posedge nclk[0]) begin
|
||||
|
||||
r1a_q <= r1a_d;
|
||||
r2a_q <= r2a_d;
|
||||
|
||||
r1d_q <= r1d_d;
|
||||
r2d_q <= r2d_d;
|
||||
|
||||
if (w_late_en_1) begin
|
||||
mem[w_addr_in_1] <= w_data_in_1;
|
||||
end
|
||||
if (w_late_en_2) begin
|
||||
mem[w_addr_in_2] <= w_data_in_2;
|
||||
end
|
||||
if (w_late_en_3) begin
|
||||
mem[w_addr_in_3] <= w_data_in_3;
|
||||
end
|
||||
if (w_late_en_4) begin
|
||||
mem[w_addr_in_4] <= w_data_in_4;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// r_late_en_x are unused in original also
|
||||
assign r1d_d = mem[r1a_q];
|
||||
assign r2d_d = mem[r2a_q];
|
||||
|
||||
assign r_data_out_1 = r1d_q;
|
||||
assign r_data_out_2 = r2d_q;
|
||||
|
||||
assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b};
|
||||
|
||||
endmodule
|
||||
@ -1,273 +0,0 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_512x16_1r1w_1(
|
||||
vdd,
|
||||
vcs,
|
||||
gnd,
|
||||
nclk,
|
||||
rd_act,
|
||||
wr_act,
|
||||
lcb_d_mode_dc,
|
||||
lcb_clkoff_dc_b,
|
||||
lcb_mpw1_dc_b,
|
||||
lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc,
|
||||
ccflush_dc,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
func_scan_in,
|
||||
func_scan_out,
|
||||
lcb_sg_0,
|
||||
lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0,
|
||||
lcb_abst_sl_thold_0,
|
||||
lcb_ary_nsl_thold_0,
|
||||
lcb_repr_sl_thold_0,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
bw,
|
||||
wr_adr,
|
||||
rd_adr,
|
||||
di,
|
||||
dout
|
||||
);
|
||||
parameter addressable_ports = 128; // number of addressable register in this array
|
||||
parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
|
||||
parameter port_bitwidth = 16; // bitwidth of ports
|
||||
parameter ways = 1; // number of ways
|
||||
|
||||
// POWER PINS
|
||||
inout vdd;
|
||||
inout vcs;
|
||||
inout gnd;
|
||||
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
|
||||
input rd_act;
|
||||
input wr_act;
|
||||
|
||||
// DC TEST PINS
|
||||
input lcb_d_mode_dc;
|
||||
input lcb_clkoff_dc_b;
|
||||
input [0:4] lcb_mpw1_dc_b;
|
||||
input lcb_mpw2_dc_b;
|
||||
input [0:4] lcb_delay_lclkr_dc;
|
||||
|
||||
input ccflush_dc;
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input func_scan_in;
|
||||
output func_scan_out;
|
||||
|
||||
input lcb_sg_0;
|
||||
input lcb_sl_thold_0_b;
|
||||
input lcb_time_sl_thold_0;
|
||||
input lcb_abst_sl_thold_0;
|
||||
input lcb_ary_nsl_thold_0;
|
||||
input lcb_repr_sl_thold_0;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:6] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:6] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
input [0:15] bw;
|
||||
input [0:8] wr_adr;
|
||||
input [0:8] rd_adr;
|
||||
input [0:15] di;
|
||||
|
||||
output [0:15] dout;
|
||||
|
||||
wire clk;
|
||||
wire [0:8] b0addra;
|
||||
wire [0:8] b0addrb;
|
||||
wire wea;
|
||||
wire web;
|
||||
wire wren_a;
|
||||
wire [0:15] w_data_in_0;
|
||||
wire [0:15] r_data_out_0_bram;
|
||||
|
||||
// Latches
|
||||
reg reset_q;
|
||||
reg [0:15] r_data_out_1_q;
|
||||
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:15] mem[0:511];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 512; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 512; j=j+1) begin: loc
|
||||
wire [0:15] dat;
|
||||
assign dat = mem[j][0:15];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign clk = nclk[0];
|
||||
|
||||
always @(posedge clk)
|
||||
begin: rlatch
|
||||
reset_q <= nclk[1];
|
||||
end
|
||||
|
||||
//wtf do they use diff addresses?
|
||||
assign b0addra[0:8] = wr_adr;
|
||||
assign b0addrb[0:8] = rd_adr;
|
||||
|
||||
// port a is a read-modify-write port
|
||||
assign wren_a = (bw != 0) & wr_act;
|
||||
assign wea = wren_a;
|
||||
assign web = 1'b0;
|
||||
assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
|
||||
assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
|
||||
assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
|
||||
assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
|
||||
assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
|
||||
assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
|
||||
assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
|
||||
assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
|
||||
assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
|
||||
assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
|
||||
assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
|
||||
assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
|
||||
assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
|
||||
assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
|
||||
assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
|
||||
assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r_data_out_1_q <= mem[b0addrb];
|
||||
if (wea) begin
|
||||
mem[b0addra] <= w_data_in_0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign r_data_out_0_bram = mem[b0addra];
|
||||
assign dout = r_data_out_1_q[0:15];
|
||||
|
||||
assign func_scan_out = func_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
|
||||
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
|
||||
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc, rd_act};
|
||||
endmodule
|
||||
@ -1,245 +0,0 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri-Lam Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_64x72_1r1w(
|
||||
vdd,
|
||||
vcs,
|
||||
gnd,
|
||||
nclk,
|
||||
sg_0,
|
||||
abst_sl_thold_0,
|
||||
ary_nsl_thold_0,
|
||||
time_sl_thold_0,
|
||||
repr_sl_thold_0,
|
||||
rd0_act,
|
||||
rd0_adr,
|
||||
do0,
|
||||
wr_act,
|
||||
wr_adr,
|
||||
di,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
ccflush_dc,
|
||||
clkoff_dc_b,
|
||||
d_mode_dc,
|
||||
mpw1_dc_b,
|
||||
mpw2_dc_b,
|
||||
delay_lclkr_dc,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp
|
||||
);
|
||||
|
||||
// Power
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout vdd;
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout vcs;
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout gnd;
|
||||
|
||||
// Clock Pervasive
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
input sg_0;
|
||||
input abst_sl_thold_0;
|
||||
input ary_nsl_thold_0;
|
||||
input time_sl_thold_0;
|
||||
input repr_sl_thold_0;
|
||||
|
||||
// Reads
|
||||
input rd0_act;
|
||||
input [0:5] rd0_adr;
|
||||
output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;
|
||||
|
||||
// Writes
|
||||
input wr_act;
|
||||
input [0:5] wr_adr;
|
||||
input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di;
|
||||
|
||||
// Scan
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
// Misc Pervasive
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input ccflush_dc;
|
||||
input clkoff_dc_b;
|
||||
input d_mode_dc;
|
||||
input [0:4] mpw1_dc_b;
|
||||
input mpw2_dc_b;
|
||||
input [0:4] delay_lclkr_dc;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
// ABIST
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:5] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:5] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
wire sreset;
|
||||
wire [0:71] tidn;
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:63] mem[0:71];
|
||||
|
||||
reg r0_e_q;
|
||||
wire r0_e_d;
|
||||
reg [0:5] r0_a_q;
|
||||
wire [0:5] r0_a_d;
|
||||
reg [0:71] r0_d_q;
|
||||
wire [0:71] r0_d_d;
|
||||
|
||||
reg w0_e_q;
|
||||
wire w0_e_d;
|
||||
reg [0:5] w0_a_q;
|
||||
wire [0:5] w0_a_d;
|
||||
reg [0:71] w0_d_q;
|
||||
wire [0:71] w0_d_d;
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 64; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 63; j=j+1) begin: loc
|
||||
wire [0:63] dat;
|
||||
wire [0:7] par;
|
||||
assign dat = mem[j][0:63];
|
||||
assign par = mem[j][0:7];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
|
||||
assign clk = nclk[0];
|
||||
assign sreset = nclk[1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r0_e_q <= rd0_act;
|
||||
r0_a_q <= rd0_adr;
|
||||
r0_d_q <= r0_e_q ? mem[r0_a_q] : 0;
|
||||
|
||||
if (w0_e_q) begin
|
||||
mem[w0_a_q] <= w0_d_q;
|
||||
end
|
||||
w0_e_q <= wr_act;
|
||||
w0_a_q <= wr_adr;
|
||||
w0_d_q <= di;
|
||||
|
||||
end
|
||||
|
||||
assign do0 = r0_d_q;
|
||||
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue