issues 13,14: single clk, no more nclk
openpowerwtf
3 years ago
parent
24d56dc84b
commit
af556071b0
@ -1,427 +0,0 @@
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#!/usr/bin/python3
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#
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# Parse table comments and create equations.
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from optparse import OptionParser
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import re
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from shutil import copyfile
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#--------------------------------------------------------------------------------------------------
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# Initialize
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TYPE_INPUT = 0
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TYPE_OUTPUT = 1
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TYPE_SKIP = 99
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lines = []
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tableMatches = []
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tableNames = []
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tableLines = []
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tables = {}
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failOnError = True
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inFile = 'test.vhdl'
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outFileExt = 'vtable'
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overwrite = True
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backupExt = 'orig'
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backup = True
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noisy = False
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quiet = False
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verilog = False
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#--------------------------------------------------------------------------------------------------
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# Handle command line
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usage = 'vtable [options] inFile'
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parser = OptionParser(usage)
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parser.add_option('-f', '--outfile', dest='outFile', help='output file, default=[inFile]' + outFileExt)
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parser.add_option('-o', '--overwrite', dest='overwrite', help='overwrite inFile, default=' + str(overwrite))
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parser.add_option('-b', '--backup', dest='backup', help='backup original file, default=' + str(backup))
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parser.add_option('-q', '--quiet', dest='quiet', action='store_true', help='quiet messages, default=' + str(quiet))
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parser.add_option('-n', '--noisy', dest='noisy', action='store_true', help='noisy messages, default=' + str(noisy))
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parser.add_option('-V', '--verilog', dest='verilog', action='store_true', help='source is verilog, default=' + str(verilog))
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options, args = parser.parse_args()
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if len(args) != 1:
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parser.error(usage)
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quit(-1)
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else:
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inFile = args[0]
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if options.overwrite == '0':
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overwrite = False
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elif options.overwrite == '1':
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overwrite == True
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if options.outFile is not None:
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parser.error('Can\'t specify outfile and overrite!')
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quit(-1)
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elif options.overwrite is not None:
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parser.error('overwrite: 0|1')
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quit(-1)
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if options.quiet is not None:
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quiet = True
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if options.noisy is not None:
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noisy = True
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if options.verilog is not None:
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verilog = True
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if options.backup == '0':
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backup = False
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elif options.backup == '1':
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backup == True
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elif options.backup is not None:
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parser.error('backup: 0|1')
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quit(-1)
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if options.outFile is not None:
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outFile = options.outFile
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elif overwrite:
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outFile = inFile
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else:
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outFile = inFile + '.' + outFileExt
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backupFile = inFile + '.' + backupExt
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#--------------------------------------------------------------------------------------------------
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# Objects
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class Signal:
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def __init__(self, name, type):
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self.name = name;
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self.type = type;
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class Table:
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def __init__(self, name):
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self.name = name
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self.source = []
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self.signals = {}
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self.signalsByCol = {}
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self.typesByCol = {}
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self.specs = [] # list of specsByCol
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self.equations = []
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self.added = False
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def validate(self):
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# check that all signals have a good type
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for col in self.signalsByCol:
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if col not in self.typesByCol:
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error('Table ' + self.name + ': no signal type for ' + self.signalsByCol[col])
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elif self.typesByCol[col] == None:
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error('Table ' + self.name + ': bad signal type (' + str(self.typesByCol[col]) + ') for ' + str(self.signalsByCol[col]))
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def makeRTL(self, form=None):
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outputsByCol = {}
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#for col,type in self.typesByCol.items():
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for col in sorted(self.typesByCol):
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type = self.typesByCol[col]
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if type == TYPE_OUTPUT:
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if col in self.signalsByCol:
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outputsByCol[col] = self.signalsByCol[col]
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else:
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print(self.signalsByCol)
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print(self.typesByCol)
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error('Table ' + self.name + ': output is specified in col ' + str(col) + ' but no signal exists')
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#for sigCol,sig in outputsByCol.items():
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for sigCol in sorted(outputsByCol):
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sig = outputsByCol[sigCol]
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if not verilog:
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line = sig + ' <= '
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else:
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line = 'assign ' + sig + ' = '
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nonzero = False
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for specsByCol in self.specs:
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terms = []
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if sigCol not in specsByCol:
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#error('* Output ' + sig + ' has no specified value for column ' + str(col))
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1 # no error, can be dontcare
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elif specsByCol[sigCol] == '1':
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for col,val in specsByCol.items():
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if col not in self.typesByCol:
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if noisy:
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error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ') - no associated signal', False) #wtf UNTIL CAN HANDLE COMMENTS AT END!!!!!!!!!!!!!!!!!!!
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elif self.typesByCol[col] == TYPE_INPUT:
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if val == '0':
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terms.append(opNot + self.signalsByCol[col])
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if nonzero and len(terms) == 1:
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line = line + ') ' + opOr + '\n (';
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elif len(terms) == 1:
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line = line + '\n ('
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nonzero = True
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elif val == '1':
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terms.append(self.signalsByCol[col])
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if nonzero and len(terms) == 1:
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line = line + ') ' + opOr + '\n (';
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elif len(terms) == 1:
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line = line + '\n ('
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nonzero = True
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else:
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error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ')')
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if len(terms) > 0:
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line = line + (' ' + opAnd + ' ').join(terms)
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if not nonzero:
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line = line + zero + ";";
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else:
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line = line + ');'
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self.equations.append(line)
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return self.equations
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def printv(self):
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self.makeRTL()
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print('\n'.join(self.equations))
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def printinfo(self):
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print('Table: ' + self.name)
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print
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for l in self.source:
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print(l)
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print
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print('Signals by column:')
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for col in sorted(self.signalsByCol):
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print('{0:>3}. {1:} ({2:}) '.format(col, self.signalsByCol[col], 'in' if self.typesByCol[col] == TYPE_INPUT else 'out'))
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#--------------------------------------------------------------------------------------------------
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# Functions
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def error(msg, quitOverride=None):
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print('*** ' + msg)
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if quitOverride == False:
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1
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elif (quitOverride == None) or failOnError:
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quit(-10)
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elif quitOverride:
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quit(-10)
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#--------------------------------------------------------------------------------------------------
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# Do something
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if not verilog:
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openBracket = '('
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closeBracket = ')'
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opAnd = 'and'
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opOr = 'or'
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opNot = 'not '
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zero = "'0'"
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tablePattern = re.compile(r'^\s*?--tbl(?:\s+([^\s]+).*$|\s*$)')
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tableGenPattern = re.compile(r'^\s*?--vtable(?:\s+([^\s]+).*$)')
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commentPattern = re.compile(r'^\s*?(--.*$|\s*$)')
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tableLinePattern = re.compile(r'^.*?--(.*)')
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namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')
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else:
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openBracket = '['
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closeBracket = ']'
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opAnd = '&'
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opOr = '|'
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opNot = '~'
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zero = "'b0"
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tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)')
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tableGenPattern = re.compile(r'^\s*?\/\/vtable(?:\s+([^\s]+).*$)')
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commentPattern = re.compile(r'^\s*?(\/\/.*$|\s*$)')
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tableLinePattern = re.compile(r'^.*?\/\/(.*)')
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namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')
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# find the lines with table spec
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try:
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inf = open(inFile)
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for i, line in enumerate(inf):
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lines.append(line.strip('\n'))
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for match in re.finditer(tablePattern, line):
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tableMatches.append(i)
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inf.close()
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except Exception as e:
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error('Error opening input file ' + inFile + '\n' + str(e), True)
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# validate matches; should be paired, nothing but comments and empties; table may be named
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# between them
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for i in range(0, len(tableMatches), 2):
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if i + 1 > len(tableMatches) - 1:
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error('Mismatched table tags.\nFound so far: ' + ', '.join(tableNames), True)
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tLines = lines[tableMatches[i]:tableMatches[i+1]+1]
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tableLines.append(tLines)
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tName = re.match(tablePattern, lines[tableMatches[i]]).groups()[0]
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if tName is None:
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tName = 'noname_' + str(tableMatches[i] + 1)
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tableNames.append(tName)
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for line in tLines:
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if not re.match(commentPattern, line):
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error('Found noncomment, nonempty line in table ' + tName + ':\n' + line, True)
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print('Found tables: ' + ', '.join(tableNames))
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# build table objects
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for table, tName in zip(tableLines, tableNames):
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print('Parsing ' + tName + '...')
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namesByCol = {}
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colsByName = {}
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bitsByCol = {}
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typesByCol = {}
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specs = []
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# parse the table - do by Table.parse()
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tLines = table[1:-1] # exclude --tbl
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for line in tLines:
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if line.strip() == '':
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continue
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try:
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spec = re.search(tableLinePattern, line).groups()[0]
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except Exception as e:
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error('Problem parsing table line:\n' + line, True)
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if len(spec) > 0:
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if spec[0] == 'n':
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for match in re.finditer(namePattern, spec[1:]):
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# col 0 is first col after n
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namesByCol[match.start()] = match.groups()[0]
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colsByName[match.groups()[0]] = match.start()
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elif spec[0] == 'b':
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for i, c in enumerate(spec[1:]):
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if c == ' ' or c == '|':
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continue
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try:
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bit = int(c)
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except:
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error('Unexpected char in bit line at position ' + str(i) + ' (' + c + ')\n' + line)
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bit = None
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if i in bitsByCol and bitsByCol[i] is not None:
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bitsByCol[i] = bitsByCol[i]*10+bit
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else:
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bitsByCol[i] = bit
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elif spec[0] == 't':
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for i, c in enumerate(spec[1:]):
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if c.lower() == 'i':
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typesByCol[i] = TYPE_INPUT
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elif c.lower() == 'o':
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typesByCol[i] = TYPE_OUTPUT
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elif c.lower() == '*':
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typesByCol[i] = TYPE_SKIP
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elif c != ' ':
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error('Unexpected char in type line at position ' + str(i) + ' (' + c + ')\n' + line)
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typesByCol[i] = None
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else:
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typesByCol[i] = None
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elif spec[0] == 's':
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specsByCol = {}
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for i, c in enumerate(spec[1:]):
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if c == '0' or c == '1':
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specsByCol[i] = c
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specs.append(specsByCol)
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else:
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#print('other:')
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#print(line)
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1
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# create table object
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# add strand to name where defined; don't combine for now into vector
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# consecutive strands belong to the last defined name
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lastName = None
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lastCol = 0
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signalsByCol = {}
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for col,name in namesByCol.items(): # load with unstranded names
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signalsByCol[col] = name
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# sort by col so consecutive columns can be easily tracked
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#for col,val in bitsByCol.items(): # update with stranded names
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for col in sorted(bitsByCol):
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val = bitsByCol[col]
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if col > lastCol + 1:
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lastName = None
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if val is None:
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lastName = None
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if col in namesByCol:
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if val is None:
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signalsByCol[col] = namesByCol[col]
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else:
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lastName = namesByCol[col]
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signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
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elif lastName is not None:
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signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
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else:
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error('Can\'t associate bit number ' + str(val) + ' in column ' + str(col) + ' with a signal name.')
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lastCol = col
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t = Table(tName)
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t.source = table
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t.signalsByCol = signalsByCol
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t.typesByCol = typesByCol
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t.specs = specs
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tables[tName] = t
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for name in tables:
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t = tables[name]
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t.validate()
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t.makeRTL()
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print()
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print('Results:')
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# find the lines with generate spec and replace them with new version
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outLines = []
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inTable = False
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for i, line in enumerate(lines):
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if not inTable:
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match = re.search(tableGenPattern, line)
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if match is not None:
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tName = match.groups(1)[0]
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if tName not in tables:
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if tName == 1:
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tName = '<blank>'
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error('Found vtable start for \'' + tName + '\' but didn\'t generate that table: line ' + str(i+1) + '\n' + line, True)
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else:
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outLines.append(line)
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outLines += tables[tName].equations
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tables[tName].added = True
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inTable = True
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else:
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outLines.append(line)
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else:
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match = re.search(tableGenPattern, line)
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if match is not None:
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if match.groups(1)[0] != tName:
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error('Found vtable end for \'' + match.groups(1)[0] + '\' but started table \'' + tName + '\': line ' + str(i+1) + '\n' + line, True)
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outLines.append(line)
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inTable = False
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else:
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1#print('stripped: ' + line)
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if backup:
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try:
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copyfile(inFile, backupFile)
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except Exception as e:
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error('Error creating backup file!\n' + str(e), True)
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try:
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of = open(outFile, 'w')
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for line in outLines:
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of.write("%s\n" % line)
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except Exception as e:
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error('Error writing output file ' + outFile + '!\n' + str(e), True)
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print('Generated ' + str(len(tables)) + ' tables: ' + ', '.join(tableNames))
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notAdded = {}
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for table in tables:
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if not tables[table].added:
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notAdded[table] = True
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print('Output file: ' + outFile)
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if backup:
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print('Backup file: ' + backupFile)
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if len(notAdded) != 0:
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error('Tables generated but not added to file! ' + ', '.join(notAdded))
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,281 +0,0 @@
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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: Tri Array Wrapper
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//
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//*****************************************************************************
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// sim version, clk1x
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`include "tri_a2o.vh"
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module tri_128x16_1r1w_1(
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vdd,
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vcs,
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gnd,
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nclk,
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rd_act,
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wr_act,
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lcb_d_mode_dc,
|
||||
lcb_clkoff_dc_b,
|
||||
lcb_mpw1_dc_b,
|
||||
lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc,
|
||||
ccflush_dc,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
func_scan_in,
|
||||
func_scan_out,
|
||||
lcb_sg_0,
|
||||
lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0,
|
||||
lcb_abst_sl_thold_0,
|
||||
lcb_ary_nsl_thold_0,
|
||||
lcb_repr_sl_thold_0,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
bw,
|
||||
wr_adr,
|
||||
rd_adr,
|
||||
di,
|
||||
dout
|
||||
);
|
||||
parameter addressable_ports = 128; // number of addressable register in this array
|
||||
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
|
||||
parameter port_bitwidth = 16; // bitwidth of ports
|
||||
parameter ways = 1; // number of ways
|
||||
|
||||
// POWER PINS
|
||||
inout vdd;
|
||||
inout vcs;
|
||||
inout gnd;
|
||||
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
|
||||
input rd_act;
|
||||
input wr_act;
|
||||
|
||||
// DC TEST PINS
|
||||
input lcb_d_mode_dc;
|
||||
input lcb_clkoff_dc_b;
|
||||
input [0:4] lcb_mpw1_dc_b;
|
||||
input lcb_mpw2_dc_b;
|
||||
input [0:4] lcb_delay_lclkr_dc;
|
||||
|
||||
input ccflush_dc;
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input func_scan_in;
|
||||
output func_scan_out;
|
||||
|
||||
input lcb_sg_0;
|
||||
input lcb_sl_thold_0_b;
|
||||
input lcb_time_sl_thold_0;
|
||||
input lcb_abst_sl_thold_0;
|
||||
input lcb_ary_nsl_thold_0;
|
||||
input lcb_repr_sl_thold_0;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:6] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:6] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
input [0:15] bw;
|
||||
input [0:6] wr_adr;
|
||||
input [0:6] rd_adr;
|
||||
input [0:15] di;
|
||||
|
||||
output [0:15] dout;
|
||||
|
||||
// tri_128x16_1r1w_1
|
||||
|
||||
// Configuration Statement for NCsim
|
||||
//for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;
|
||||
|
||||
wire clk;
|
||||
wire [0:8] b0addra;
|
||||
wire [0:8] b0addrb;
|
||||
wire wea;
|
||||
wire web;
|
||||
wire wren_a;
|
||||
wire [0:15] w_data_in_0;
|
||||
wire [0:15] r_data_out_0_bram;
|
||||
|
||||
// Latches
|
||||
reg reset_q;
|
||||
reg [0:15] r_data_out_1_q;
|
||||
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:15] mem[0:127];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 128; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 128; j=j+1) begin: loc
|
||||
wire [0:15] dat;
|
||||
assign dat = mem[j][0:15];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign clk = nclk[0];
|
||||
|
||||
always @(posedge clk)
|
||||
begin: rlatch
|
||||
reset_q <= nclk[1];
|
||||
end
|
||||
|
||||
assign b0addra[2:8] = wr_adr;
|
||||
assign b0addrb[2:8] = rd_adr;
|
||||
|
||||
// Unused Address Bits
|
||||
assign b0addra[0:1] = 2'b00;
|
||||
assign b0addrb[0:1] = 2'b00;
|
||||
|
||||
// port a is a read-modify-write port
|
||||
assign wren_a = (bw != 0) & wr_act;
|
||||
assign wea = wren_a;
|
||||
assign web = 1'b0;
|
||||
assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
|
||||
assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
|
||||
assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
|
||||
assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
|
||||
assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
|
||||
assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
|
||||
assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
|
||||
assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
|
||||
assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
|
||||
assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
|
||||
assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
|
||||
assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
|
||||
assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
|
||||
assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
|
||||
assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
|
||||
assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r_data_out_1_q <= mem[b0addrb];
|
||||
if (wea) begin
|
||||
mem[b0addra] <= w_data_in_0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign r_data_out_0_bram = mem[b0addra];
|
||||
assign dout = r_data_out_1_q[0:15];
|
||||
|
||||
assign func_scan_out = func_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
|
||||
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
|
||||
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc, rd_act};
|
||||
endmodule
|
||||
@ -1,157 +0,0 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri-Lam Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_144x78_2r4w(
|
||||
// Inputs
|
||||
// Power
|
||||
inout vdd,
|
||||
inout gnd,
|
||||
// Clock & Scan
|
||||
input [0:`NCLK_WIDTH-1] nclk,
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// Pervasive
|
||||
//-------------------------------------------------------------------
|
||||
input delay_lclkr_dc,
|
||||
input mpw1_dc_b,
|
||||
input mpw2_dc_b,
|
||||
input func_sl_force,
|
||||
input func_sl_thold_0_b,
|
||||
input func_slp_sl_force,
|
||||
input func_slp_sl_thold_0_b,
|
||||
input sg_0,
|
||||
input scan_in,
|
||||
output scan_out,
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// Read Port
|
||||
//-------------------------------------------------------------------
|
||||
input r_late_en_1,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1,
|
||||
output [64-`GPR_WIDTH:77] r_data_out_1,
|
||||
input r_late_en_2,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2,
|
||||
output [64-`GPR_WIDTH:77] r_data_out_2,
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// Write Port
|
||||
//-------------------------------------------------------------------
|
||||
input w_late_en_1,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_1,
|
||||
input w_late_en_2,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_2,
|
||||
input w_late_en_3,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_3,
|
||||
input w_late_en_4,
|
||||
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4,
|
||||
input [64-`GPR_WIDTH:77] w_data_in_4
|
||||
);
|
||||
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [64-`GPR_WIDTH:77] mem[0:143];
|
||||
|
||||
reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
|
||||
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d;
|
||||
reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;
|
||||
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d;
|
||||
|
||||
reg [64-`GPR_WIDTH:77] r1d_q;
|
||||
wire [64-`GPR_WIDTH:77] r1d_d;
|
||||
reg [64-`GPR_WIDTH:77] r2d_q;
|
||||
wire [64-`GPR_WIDTH:77] r2d_d;
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 144; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 144; j=j+1) begin: loc
|
||||
wire [64-`GPR_WIDTH:63] dat;
|
||||
wire [0:7] par;
|
||||
// 4b0
|
||||
assign dat = mem[j][64-`GPR_WIDTH:63];
|
||||
assign par = mem[j][64:63 + `GPR_WIDTH/8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign r1a_d = r_addr_in_1;
|
||||
assign r2a_d = r_addr_in_2;
|
||||
|
||||
always @(posedge nclk[0]) begin
|
||||
|
||||
r1a_q <= r1a_d;
|
||||
r2a_q <= r2a_d;
|
||||
|
||||
r1d_q <= r1d_d;
|
||||
r2d_q <= r2d_d;
|
||||
|
||||
if (w_late_en_1) begin
|
||||
mem[w_addr_in_1] <= w_data_in_1;
|
||||
end
|
||||
if (w_late_en_2) begin
|
||||
mem[w_addr_in_2] <= w_data_in_2;
|
||||
end
|
||||
if (w_late_en_3) begin
|
||||
mem[w_addr_in_3] <= w_data_in_3;
|
||||
end
|
||||
if (w_late_en_4) begin
|
||||
mem[w_addr_in_4] <= w_data_in_4;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// r_late_en_x are unused in original also
|
||||
assign r1d_d = mem[r1a_q];
|
||||
assign r2d_d = mem[r2a_q];
|
||||
|
||||
assign r_data_out_1 = r1d_q;
|
||||
assign r_data_out_2 = r2d_q;
|
||||
|
||||
assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b};
|
||||
|
||||
endmodule
|
||||
@ -1,273 +0,0 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_512x16_1r1w_1(
|
||||
vdd,
|
||||
vcs,
|
||||
gnd,
|
||||
nclk,
|
||||
rd_act,
|
||||
wr_act,
|
||||
lcb_d_mode_dc,
|
||||
lcb_clkoff_dc_b,
|
||||
lcb_mpw1_dc_b,
|
||||
lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc,
|
||||
ccflush_dc,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
func_scan_in,
|
||||
func_scan_out,
|
||||
lcb_sg_0,
|
||||
lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0,
|
||||
lcb_abst_sl_thold_0,
|
||||
lcb_ary_nsl_thold_0,
|
||||
lcb_repr_sl_thold_0,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
bw,
|
||||
wr_adr,
|
||||
rd_adr,
|
||||
di,
|
||||
dout
|
||||
);
|
||||
parameter addressable_ports = 128; // number of addressable register in this array
|
||||
parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
|
||||
parameter port_bitwidth = 16; // bitwidth of ports
|
||||
parameter ways = 1; // number of ways
|
||||
|
||||
// POWER PINS
|
||||
inout vdd;
|
||||
inout vcs;
|
||||
inout gnd;
|
||||
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
|
||||
input rd_act;
|
||||
input wr_act;
|
||||
|
||||
// DC TEST PINS
|
||||
input lcb_d_mode_dc;
|
||||
input lcb_clkoff_dc_b;
|
||||
input [0:4] lcb_mpw1_dc_b;
|
||||
input lcb_mpw2_dc_b;
|
||||
input [0:4] lcb_delay_lclkr_dc;
|
||||
|
||||
input ccflush_dc;
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input func_scan_in;
|
||||
output func_scan_out;
|
||||
|
||||
input lcb_sg_0;
|
||||
input lcb_sl_thold_0_b;
|
||||
input lcb_time_sl_thold_0;
|
||||
input lcb_abst_sl_thold_0;
|
||||
input lcb_ary_nsl_thold_0;
|
||||
input lcb_repr_sl_thold_0;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:6] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:6] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
input [0:15] bw;
|
||||
input [0:8] wr_adr;
|
||||
input [0:8] rd_adr;
|
||||
input [0:15] di;
|
||||
|
||||
output [0:15] dout;
|
||||
|
||||
wire clk;
|
||||
wire [0:8] b0addra;
|
||||
wire [0:8] b0addrb;
|
||||
wire wea;
|
||||
wire web;
|
||||
wire wren_a;
|
||||
wire [0:15] w_data_in_0;
|
||||
wire [0:15] r_data_out_0_bram;
|
||||
|
||||
// Latches
|
||||
reg reset_q;
|
||||
reg [0:15] r_data_out_1_q;
|
||||
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:15] mem[0:511];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 512; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 512; j=j+1) begin: loc
|
||||
wire [0:15] dat;
|
||||
assign dat = mem[j][0:15];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign clk = nclk[0];
|
||||
|
||||
always @(posedge clk)
|
||||
begin: rlatch
|
||||
reset_q <= nclk[1];
|
||||
end
|
||||
|
||||
//wtf do they use diff addresses?
|
||||
assign b0addra[0:8] = wr_adr;
|
||||
assign b0addrb[0:8] = rd_adr;
|
||||
|
||||
// port a is a read-modify-write port
|
||||
assign wren_a = (bw != 0) & wr_act;
|
||||
assign wea = wren_a;
|
||||
assign web = 1'b0;
|
||||
assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
|
||||
assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
|
||||
assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
|
||||
assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
|
||||
assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
|
||||
assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
|
||||
assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
|
||||
assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
|
||||
assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
|
||||
assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
|
||||
assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
|
||||
assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
|
||||
assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
|
||||
assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
|
||||
assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
|
||||
assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r_data_out_1_q <= mem[b0addrb];
|
||||
if (wea) begin
|
||||
mem[b0addra] <= w_data_in_0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign r_data_out_0_bram = mem[b0addra];
|
||||
assign dout = r_data_out_1_q[0:15];
|
||||
|
||||
assign func_scan_out = func_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
|
||||
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
|
||||
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
|
||||
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
|
||||
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc, rd_act};
|
||||
endmodule
|
||||
@ -1,245 +0,0 @@
|
||||
// © IBM Corp. 2022
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
//*****************************************************************************
|
||||
// Description: Tri-Lam Array Wrapper
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
// sim version, clk1x
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_64x72_1r1w(
|
||||
vdd,
|
||||
vcs,
|
||||
gnd,
|
||||
nclk,
|
||||
sg_0,
|
||||
abst_sl_thold_0,
|
||||
ary_nsl_thold_0,
|
||||
time_sl_thold_0,
|
||||
repr_sl_thold_0,
|
||||
rd0_act,
|
||||
rd0_adr,
|
||||
do0,
|
||||
wr_act,
|
||||
wr_adr,
|
||||
di,
|
||||
abst_scan_in,
|
||||
abst_scan_out,
|
||||
time_scan_in,
|
||||
time_scan_out,
|
||||
repr_scan_in,
|
||||
repr_scan_out,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
ccflush_dc,
|
||||
clkoff_dc_b,
|
||||
d_mode_dc,
|
||||
mpw1_dc_b,
|
||||
mpw2_dc_b,
|
||||
delay_lclkr_dc,
|
||||
lcb_bolt_sl_thold_0,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
abist_di,
|
||||
abist_bw_odd,
|
||||
abist_bw_even,
|
||||
abist_wr_adr,
|
||||
wr_abst_act,
|
||||
abist_rd0_adr,
|
||||
rd0_abst_act,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_ena_1,
|
||||
abist_g8t_rd0_comp_ena,
|
||||
abist_raw_dc_b,
|
||||
obs0_abist_cmp
|
||||
);
|
||||
|
||||
// Power
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout vdd;
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout vcs;
|
||||
(* analysis_not_referenced="true" *)
|
||||
inout gnd;
|
||||
|
||||
// Clock Pervasive
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
input sg_0;
|
||||
input abst_sl_thold_0;
|
||||
input ary_nsl_thold_0;
|
||||
input time_sl_thold_0;
|
||||
input repr_sl_thold_0;
|
||||
|
||||
// Reads
|
||||
input rd0_act;
|
||||
input [0:5] rd0_adr;
|
||||
output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;
|
||||
|
||||
// Writes
|
||||
input wr_act;
|
||||
input [0:5] wr_adr;
|
||||
input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di;
|
||||
|
||||
// Scan
|
||||
input abst_scan_in;
|
||||
output abst_scan_out;
|
||||
input time_scan_in;
|
||||
output time_scan_out;
|
||||
input repr_scan_in;
|
||||
output repr_scan_out;
|
||||
|
||||
// Misc Pervasive
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
input ccflush_dc;
|
||||
input clkoff_dc_b;
|
||||
input d_mode_dc;
|
||||
input [0:4] mpw1_dc_b;
|
||||
input mpw2_dc_b;
|
||||
input [0:4] delay_lclkr_dc;
|
||||
|
||||
// BOLT-ON
|
||||
input lcb_bolt_sl_thold_0;
|
||||
input pc_bo_enable_2; // general bolt-on enable
|
||||
input pc_bo_reset; // reset
|
||||
input pc_bo_unload; // unload sticky bits
|
||||
input pc_bo_repair; // execute sticky bit decode
|
||||
input pc_bo_shdata; // shift data for timing write and diag loop
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
// ABIST
|
||||
input [0:3] abist_di;
|
||||
input abist_bw_odd;
|
||||
input abist_bw_even;
|
||||
input [0:5] abist_wr_adr;
|
||||
input wr_abst_act;
|
||||
input [0:5] abist_rd0_adr;
|
||||
input rd0_abst_act;
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_ena_1;
|
||||
input abist_g8t_rd0_comp_ena;
|
||||
input abist_raw_dc_b;
|
||||
input [0:3] obs0_abist_cmp;
|
||||
|
||||
wire sreset;
|
||||
wire [0:71] tidn;
|
||||
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
|
||||
// sim array
|
||||
reg [0:63] mem[0:71];
|
||||
|
||||
reg r0_e_q;
|
||||
wire r0_e_d;
|
||||
reg [0:5] r0_a_q;
|
||||
wire [0:5] r0_a_d;
|
||||
reg [0:71] r0_d_q;
|
||||
wire [0:71] r0_d_d;
|
||||
|
||||
reg w0_e_q;
|
||||
wire w0_e_d;
|
||||
reg [0:5] w0_a_q;
|
||||
wire [0:5] w0_a_d;
|
||||
reg [0:71] w0_d_q;
|
||||
wire [0:71] w0_d_d;
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 64; i = i + 1)
|
||||
mem[i] = 0;
|
||||
end
|
||||
|
||||
//wtf:icarus $dumpvars cannot dump a vpiMemory
|
||||
generate
|
||||
genvar j;
|
||||
for (j = 0; j < 63; j=j+1) begin: loc
|
||||
wire [0:63] dat;
|
||||
wire [0:7] par;
|
||||
assign dat = mem[j][0:63];
|
||||
assign par = mem[j][0:7];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
|
||||
assign clk = nclk[0];
|
||||
assign sreset = nclk[1];
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
r0_e_q <= rd0_act;
|
||||
r0_a_q <= rd0_adr;
|
||||
r0_d_q <= r0_e_q ? mem[r0_a_q] : 0;
|
||||
|
||||
if (w0_e_q) begin
|
||||
mem[w0_a_q] <= w0_d_q;
|
||||
end
|
||||
w0_e_q <= wr_act;
|
||||
w0_a_q <= wr_adr;
|
||||
w0_d_q <= di;
|
||||
|
||||
end
|
||||
|
||||
assign do0 = r0_d_q;
|
||||
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff