You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
46 lines
1.0 KiB
Makefile
46 lines
1.0 KiB
Makefile
2 years ago
|
# a2o smt2 tb
|
||
|
|
# make -f Makefile.icarus build # rebuild and sim and fst
|
||
|
|
# make -f Makefile.icarus run # sim and fst
|
||
|
|
# make -f Makefile.icarus # sim
|
||
|
|
|
||
|
2 years ago
|
SIM_BUILD ?= build_smt
|
||
|
2 years ago
|
SIM ?= icarus
|
||
|
|
|
||
|
|
# options
|
||
|
|
#COCOTB_HDL_TIMEUNIT ?= 1ns
|
||
|
|
#COCOTB_HDL_TIMEPRECISION ?= 1ps
|
||
|
|
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
|
||
|
|
|
||
|
|
# icarus
|
||
|
|
#
|
||
|
|
# includes are needed for *.vh
|
||
|
|
# unisims is for FPGA RAMs
|
||
|
|
# coco forces -g2012 for some reason, and appends it after COMPILE_ARGS below! issue #781
|
||
|
|
|
||
|
|
VERILOG_ROOT = ../../verilog
|
||
|
|
|
||
|
2 years ago
|
COMPILE_ARGS = -I$(VERILOG_ROOT)/smt -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
|
||
|
2 years ago
|
|
||
|
|
# other options
|
||
|
|
|
||
|
|
# rtl
|
||
|
|
TOPLEVEL_LANG = verilog
|
||
|
|
# top-level to enable trace, etc.
|
||
|
|
VERILOG_SOURCES = ./cocotb_icarus.v
|
||
|
|
TOPLEVEL = cocotb_icarus
|
||
|
|
|
||
|
|
# python test
|
||
|
|
MODULE = tb
|
||
|
2 years ago
|
TESTCASE = tb_smt
|
||
|
2 years ago
|
|
||
|
|
# cocotb make rules
|
||
|
|
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||
|
|
|
||
|
|
build: clean sim fst
|
||
|
|
|
||
|
|
run: sim fst
|
||
|
|
|
||
|
|
fst:
|
||
|
2 years ago
|
vcd2fst a2ocore.vcd a2ocore_smt.fst
|
||
|
|
rm a2ocore.vcd
|