a2o/dev/verilog/trilib/tri_lcbs.v

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`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME    : tri_lcbs.v
// *! DESCRIPTION : Wrapper for slat LCB
// *!****************************************************************

`include "tri_a2o.vh"

//wtf this should be changed to output clk,rst instead of lclk; think it's only for alternate ring lats?
module tri_lcbs (
   vd,
   gd,
   delay_lclkr,
   clk,
   rst,
   force_t,
   thold_b,
   dclk,
   lclk
);
   inout      vd;
   inout      gd;
   input      delay_lclkr;
   input      clk;
   input      rst;
   input      force_t;
   input      thold_b;
   output     dclk;
   output[0:`NCLK_WIDTH-1]  lclk;

   //  tri_lcbs

   (* analysis_not_referenced="true" *)
   wire       unused;

   assign unused = vd | gd | delay_lclkr | force_t;

   // No scan chain in this methodology
   assign dclk = thold_b;
   assign lclk = {clk, rst, {`NCLK_WIDTH-2{1'b0}}};
endmodule