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Verilog

2 years ago
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
//********************************************************************
//*
//* TITLE:
//*
//* NAME: c.v
//*
//*********************************************************************
`timescale 1 ns / 1 ns
// For RLMs & Top-level only
(* recursive_synthesis="0" *)
module c(
`include "tri_a2o.vh"
// inout vcs,
// inout vdd,
// inout gnd,
input clk,
input rst,
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input scan_in,
output scan_out,
// Pervasive clock control
input an_ac_rtim_sl_thold_8,
input an_ac_func_sl_thold_8,
input an_ac_func_nsl_thold_8,
input an_ac_ary_nsl_thold_8,
input an_ac_sg_8,
input an_ac_fce_8,
input [0:7] an_ac_abst_scan_in,
// L2 STCX complete
input [0:`THREADS-1] an_ac_stcx_complete,
input [0:`THREADS-1] an_ac_stcx_pass,
// ICBI ACK Interface
input an_ac_icbi_ack,
input [0:1] an_ac_icbi_ack_thread,
// Back invalidate interface
input an_ac_back_inv,
input [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr,
input [0:4] an_ac_back_inv_target, // connect to bit(0)
input an_ac_back_inv_local,
input an_ac_back_inv_lbit,
input an_ac_back_inv_gs,
input an_ac_back_inv_ind,
input [0:7] an_ac_back_inv_lpar_id,
output ac_an_back_inv_reject,
output [0:7] ac_an_lpar_id,
// L2 Reload Inputs
input an_ac_reld_data_vld, // reload data is coming next cycle
input [0:4] an_ac_reld_core_tag, // reload data destinatoin tag (which load queue)
input [0:127] an_ac_reld_data, // Reload Data
input [58:59] an_ac_reld_qw, // quadword address of reload data beat
input an_ac_reld_ecc_err, // Reload Data contains a Correctable ECC error
input an_ac_reld_ecc_err_ue, // Reload Data contains an Uncorrectable ECC error
input an_ac_reld_data_coming,
input an_ac_reld_ditc,
input an_ac_reld_crit_qw,
input an_ac_reld_l1_dump,
input [0:3] an_ac_req_spare_ctrl_a1, // spare control bits from L2
// load/store credit control
input an_ac_flh2l2_gate, // Gate L1 Hit forwarding SPR config bit
input an_ac_req_ld_pop, // credit for a load (L2 can take a load command)
input an_ac_req_st_pop, // credit for a store (L2 can take a store command)
input an_ac_req_st_gather, // credit for a store due to L2 gathering of store commands
input [0:`THREADS-1] an_ac_sync_ack,
//SCOM Satellite
input [0:3] an_ac_scom_sat_id,
input an_ac_scom_dch,
input an_ac_scom_cch,
output ac_an_scom_dch,
output ac_an_scom_cch,
// FIR and Error Signals
output [0:`THREADS-1] ac_an_special_attn,
output [0:2] ac_an_checkstop,
output [0:2] ac_an_local_checkstop,
output [0:2] ac_an_recov_err,
output ac_an_trace_error,
output ac_an_livelock_active,
input an_ac_checkstop,
input [0:`THREADS-1] an_ac_external_mchk,
// Perfmon Event Bus
output [0:4*`THREADS-1] ac_an_event_bus0,
output [0:4*`THREADS-1] ac_an_event_bus1,
// Reset related
input an_ac_reset_1_complete,
input an_ac_reset_2_complete,
input an_ac_reset_3_complete,
input an_ac_reset_wd_complete,
// Power Management
output [0:`THREADS-1] ac_an_pm_thread_running,
input [0:`THREADS-1] an_ac_pm_thread_stop,
input [0:`THREADS-1] an_ac_pm_fetch_halt,
output ac_an_power_managed,
output ac_an_rvwinkle_mode,
// Clock, Test, and LCB Controls
input an_ac_gsd_test_enable_dc,
input an_ac_gsd_test_acmode_dc,
input an_ac_ccflush_dc,
input an_ac_ccenable_dc,
input an_ac_lbist_en_dc,
input an_ac_lbist_ip_dc,
input an_ac_lbist_ac_mode_dc,
input an_ac_scan_diag_dc,
input an_ac_scan_dis_dc_b,
//Thold input to clock control macro
input [0:8] an_ac_scan_type_dc,
// Pervasive
output ac_an_reset_1_request,
output ac_an_reset_2_request,
output ac_an_reset_3_request,
output ac_an_reset_wd_request,
input an_ac_lbist_ary_wrt_thru_dc,
input [0:`THREADS-1] an_ac_reservation_vld,
input [0:`THREADS-1] an_ac_sleep_en,
input [0:`THREADS-1] an_ac_ext_interrupt,
input [0:`THREADS-1] an_ac_crit_interrupt,
input [0:`THREADS-1] an_ac_perf_interrupt,
input [0:`THREADS-1] an_ac_hang_pulse,
input an_ac_tb_update_enable,
input an_ac_tb_update_pulse,
input [0:3] an_ac_chipid_dc,
input [0:7] an_ac_coreid,
output [0:`THREADS-1] ac_an_machine_check,
input an_ac_debug_stop,
output [0:`THREADS-1] ac_an_debug_trigger,
input [0:`THREADS-1] an_ac_uncond_dbg_event,
output [0:31] ac_an_debug_bus,
output ac_an_coretrace_first_valid, // coretrace_ctrls[0]
output ac_an_coretrace_valid, // coretrace_ctrls[1]
output [0:1] ac_an_coretrace_type, // coretrace_ctrls[2:3]
// L2 Outputs
output ac_an_req_pwr_token, // power token for command coming next cycle
output ac_an_req, // command request valid
output [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra, // real address for request
output [0:5] ac_an_req_ttype, // command (transaction) type
output [0:2] ac_an_req_thread, // encoded thread ID
output ac_an_req_wimg_w, // write-through
output ac_an_req_wimg_i, // cache-inhibited
output ac_an_req_wimg_m, // memory coherence required
output ac_an_req_wimg_g, // guarded memory
output [0:3] ac_an_req_user_defined, // User Defined Bits
output [0:3] ac_an_req_spare_ctrl_a0, // Spare bits
output [0:4] ac_an_req_ld_core_tag, // load command tag (which load Q)
output [0:2] ac_an_req_ld_xfr_len, // transfer length for non-cacheable load
output [0:31] ac_an_st_byte_enbl, // byte enables for store data
output [0:255] ac_an_st_data, // store data
output ac_an_req_endian, // endian mode (0=big endian, 1=little endian)
output ac_an_st_data_pwr_token // store data power token
);
`ifndef FLOAT_TYPE
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parameter float_type = 1;
`else
parameter float_type = `FLOAT_TYPE;
`endif
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// I$
// Cache inject
wire iu_pc_err_icache_parity;
wire iu_pc_err_icachedir_parity;
wire iu_pc_err_icachedir_multihit;
wire iu_pc_err_ierat_multihit;
wire iu_pc_err_ierat_parity;
wire pc_iu_inj_icache_parity;
wire pc_iu_inj_icachedir_parity;
wire pc_iu_init_reset;
// spr ring
wire iu_slowspr_val_out;
wire iu_slowspr_rw_out;
wire [0:1] iu_slowspr_etid_out;
wire [0:9] iu_slowspr_addr_out;
wire [64-`GPR_WIDTH:63] iu_slowspr_data_out;
wire iu_slowspr_done_out;
wire iu_slowspr_val_in;
wire iu_slowspr_rw_in;
wire [0:1] iu_slowspr_etid_in;
wire [0:9] iu_slowspr_addr_in;
wire [64-`GPR_WIDTH:63] iu_slowspr_data_in;
wire iu_slowspr_done_in;
wire xu_slowspr_val_out;
wire xu_slowspr_rw_out;
wire [0:1] xu_slowspr_etid_out;
wire [0:9] xu_slowspr_addr_out;
wire [64-`GPR_WIDTH:63] xu_slowspr_data_out;
wire xu_slowspr_val_in;
wire xu_slowspr_rw_in;
wire [0:1] xu_slowspr_etid_in;
wire [0:9] xu_slowspr_addr_in;
wire [64-`GPR_WIDTH:63] xu_slowspr_data_in;
wire xu_slowspr_done_in;
wire lq_slowspr_val_out;
wire lq_slowspr_rw_out;
wire [0:1] lq_slowspr_etid_out;
wire [0:9] lq_slowspr_addr_out;
wire [64-`GPR_WIDTH:63] lq_slowspr_data_out;
wire lq_slowspr_done_out;
wire lq_slowspr_val_in;
wire lq_slowspr_rw_in;
wire [0:1] lq_slowspr_etid_in;
wire [0:9] lq_slowspr_addr_in;
wire [64-`GPR_WIDTH:63] lq_slowspr_data_in;
wire lq_slowspr_done_in;
wire pc_slowspr_val_out;
wire pc_slowspr_rw_out;
wire [0:1] pc_slowspr_etid_out;
wire [0:9] pc_slowspr_addr_out;
wire [64-`GPR_WIDTH:63] pc_slowspr_data_out;
wire pc_slowspr_done_out;
wire pc_slowspr_val_in;
wire pc_slowspr_rw_in;
wire [0:1] pc_slowspr_etid_in;
wire [0:9] pc_slowspr_addr_in;
wire [64-`GPR_WIDTH:63] pc_slowspr_data_in;
wire pc_slowspr_done_in;
wire fu_slowspr_val_out;
wire fu_slowspr_rw_out;
wire [0:1] fu_slowspr_etid_out;
wire [0:9] fu_slowspr_addr_out;
wire [64-`GPR_WIDTH:63] fu_slowspr_data_out;
wire fu_slowspr_done_out;
wire fu_slowspr_val_in;
wire fu_slowspr_rw_in;
wire [0:1] fu_slowspr_etid_in;
wire [0:9] fu_slowspr_addr_in;
wire [64-`GPR_WIDTH:63] fu_slowspr_data_in;
wire fu_slowspr_done_in;
wire mm_slowspr_val_out;
wire mm_slowspr_rw_out;
wire [0:1] mm_slowspr_etid_out;
wire [0:9] mm_slowspr_addr_out;
wire [64-`GPR_WIDTH:63] mm_slowspr_data_out;
wire mm_slowspr_done_out;
wire mm_slowspr_val_in;
wire mm_slowspr_rw_in;
wire [0:1] mm_slowspr_etid_in;
wire [0:9] mm_slowspr_addr_in;
wire [64-`GPR_WIDTH:63] mm_slowspr_data_in;
wire mm_slowspr_done_in;
// XU-IU interface
wire xu_iu_hid_mmu_mode;
// IU-ERAT interface
wire iu_mm_ierat_req;
wire iu_mm_ierat_req_nonspec;
wire [0:51] iu_mm_ierat_epn;
wire [0:`THREADS-1] iu_mm_ierat_thdid;
wire [0:3] iu_mm_ierat_state;
wire [0:13] iu_mm_ierat_tid;
wire [0:`THREADS-1] iu_mm_ierat_flush;
wire [0:`THREADS-1] iu_mm_perf_itlb;
wire [0:4] mm_iu_ierat_rel_val;
wire [0:131] mm_iu_ierat_rel_data;
wire [0:13] mm_iu_t0_ierat_pid;
wire [0:19] mm_iu_t0_ierat_mmucr0;
`ifndef THREADS1
wire [0:13] mm_iu_t1_ierat_pid;
wire [0:19] mm_iu_t1_ierat_mmucr0;
`endif
wire mm_iu_tlbwe_binv;
wire [0:5] cp_mm_except_taken_t0;
`ifndef THREADS1
wire [0:5] cp_mm_except_taken_t1;
`endif
wire [0:17] iu_mm_ierat_mmucr0;
wire [0:`THREADS-1] iu_mm_ierat_mmucr0_we;
wire [0:8] mm_iu_ierat_mmucr1;
wire [0:3] iu_mm_ierat_mmucr1;
wire [0:`THREADS-1] iu_mm_ierat_mmucr1_we;
wire mm_iu_ierat_snoop_coming;
wire mm_iu_ierat_snoop_val;
wire [0:25] mm_iu_ierat_snoop_attr;
wire [(62-`EFF_IFAR_ARCH):51] mm_iu_ierat_snoop_vpn;
wire iu_mm_ierat_snoop_ack;
wire [0:`THREADS-1] iu_mm_hold_ack;
wire [0:`THREADS-1] iu_mm_bus_snoop_hold_ack;
wire [0:`THREADS-1] mm_iu_bus_snoop_hold_req;
wire [0:`THREADS-1] mm_iu_bus_snoop_hold_done;
wire [0:`THREADS-1] mm_iu_tlbi_complete;
wire [0:`THREADS-1] mm_iu_hold_req;
wire [0:`THREADS-1] mm_iu_hold_done;
wire [0:`THREADS-1] mm_iu_flush_req;
// IU-LQ interface
wire [0:`THREADS-1] iu_lq_request;
wire [0:1] iu_lq_cTag;
wire [64-`REAL_IFAR_WIDTH:59] iu_lq_ra;
wire [0:4] iu_lq_wimge;
wire [0:3] iu_lq_userdef;
wire [0:`THREADS-1] lq_iu_icbi_val;
wire [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr;
wire [0:`THREADS-1] iu_lq_icbi_complete;
wire lq_iu_ici_val;
// IU-RV interface
wire iu_rv_iu6_t0_i0_vld;
wire iu_rv_iu6_t0_i0_act;
wire iu_rv_iu6_t0_i0_rte_lq;
wire iu_rv_iu6_t0_i0_rte_sq;
wire iu_rv_iu6_t0_i0_rte_fx0;
wire iu_rv_iu6_t0_i0_rte_fx1;
wire iu_rv_iu6_t0_i0_rte_axu0;
wire iu_rv_iu6_t0_i0_rte_axu1;
wire [0:31] iu_rv_iu6_t0_i0_instr;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_ifar;
wire [0:2] iu_rv_iu6_t0_i0_ucode;
wire iu_rv_iu6_t0_i0_2ucode;
wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i0_ucode_cnt;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_itag;
wire iu_rv_iu6_t0_i0_ord;
wire iu_rv_iu6_t0_i0_cord;
wire iu_rv_iu6_t0_i0_spec;
wire iu_rv_iu6_t0_i0_t1_v;
wire [0:2] iu_rv_iu6_t0_i0_t1_t;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_p;
wire iu_rv_iu6_t0_i0_t2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_p;
wire [0:2] iu_rv_iu6_t0_i0_t2_t;
wire iu_rv_iu6_t0_i0_t3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_p;
wire [0:2] iu_rv_iu6_t0_i0_t3_t;
wire iu_rv_iu6_t0_i0_s1_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_p;
wire [0:2] iu_rv_iu6_t0_i0_s1_t;
wire iu_rv_iu6_t0_i0_s2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_p;
wire [0:2] iu_rv_iu6_t0_i0_s2_t;
wire iu_rv_iu6_t0_i0_s3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_p;
wire [0:2] iu_rv_iu6_t0_i0_s3_t;
wire [0:3] iu_rv_iu6_t0_i0_ilat;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_bta;
wire iu_rv_iu6_t0_i0_bta_val;
wire iu_rv_iu6_t0_i0_br_pred;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_fusion;
wire [0:2] iu_rv_iu6_t0_i0_ls_ptr;
wire [0:17] iu_rv_iu6_t0_i0_gshare;
wire iu_rv_iu6_t0_i0_bh_update;
wire iu_rv_iu6_t0_i0_isLoad;
wire iu_rv_iu6_t0_i0_isStore;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s3_itag;
wire iu_rv_iu6_t0_i1_vld;
wire iu_rv_iu6_t0_i1_act;
wire iu_rv_iu6_t0_i1_rte_lq;
wire iu_rv_iu6_t0_i1_rte_sq;
wire iu_rv_iu6_t0_i1_rte_fx0;
wire iu_rv_iu6_t0_i1_rte_fx1;
wire iu_rv_iu6_t0_i1_rte_axu0;
wire iu_rv_iu6_t0_i1_rte_axu1;
wire [0:31] iu_rv_iu6_t0_i1_instr;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_ifar;
wire [0:2] iu_rv_iu6_t0_i1_ucode;
wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i1_ucode_cnt;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_itag;
wire iu_rv_iu6_t0_i1_ord;
wire iu_rv_iu6_t0_i1_cord;
wire iu_rv_iu6_t0_i1_spec;
wire iu_rv_iu6_t0_i1_t1_v;
wire [0:2] iu_rv_iu6_t0_i1_t1_t;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_p;
wire iu_rv_iu6_t0_i1_t2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_p;
wire [0:2] iu_rv_iu6_t0_i1_t2_t;
wire iu_rv_iu6_t0_i1_t3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_p;
wire [0:2] iu_rv_iu6_t0_i1_t3_t;
wire iu_rv_iu6_t0_i1_s1_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_p;
wire [0:2] iu_rv_iu6_t0_i1_s1_t;
wire iu_rv_iu6_t0_i1_s1_dep_hit;
wire iu_rv_iu6_t0_i1_s2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_p;
wire [0:2] iu_rv_iu6_t0_i1_s2_t;
wire iu_rv_iu6_t0_i1_s2_dep_hit;
wire iu_rv_iu6_t0_i1_s3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p;
wire [0:2] iu_rv_iu6_t0_i1_s3_t;
wire iu_rv_iu6_t0_i1_s3_dep_hit;
wire [0:3] iu_rv_iu6_t0_i1_ilat;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_bta;
wire iu_rv_iu6_t0_i1_bta_val;
wire iu_rv_iu6_t0_i1_br_pred;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_fusion;
wire [0:2] iu_rv_iu6_t0_i1_ls_ptr;
wire [0:17] iu_rv_iu6_t0_i1_gshare;
wire iu_rv_iu6_t0_i1_bh_update;
wire iu_rv_iu6_t0_i1_isLoad;
wire iu_rv_iu6_t0_i1_isStore;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag;
`ifndef THREADS1
wire iu_rv_iu6_t1_i0_vld;
wire iu_rv_iu6_t1_i0_act;
wire iu_rv_iu6_t1_i0_rte_lq;
wire iu_rv_iu6_t1_i0_rte_sq;
wire iu_rv_iu6_t1_i0_rte_fx0;
wire iu_rv_iu6_t1_i0_rte_fx1;
wire iu_rv_iu6_t1_i0_rte_axu0;
wire iu_rv_iu6_t1_i0_rte_axu1;
wire [0:31] iu_rv_iu6_t1_i0_instr;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_ifar;
wire [0:2] iu_rv_iu6_t1_i0_ucode;
wire iu_rv_iu6_t1_i0_2ucode;
wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i0_ucode_cnt;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag;
wire iu_rv_iu6_t1_i0_ord;
wire iu_rv_iu6_t1_i0_cord;
wire iu_rv_iu6_t1_i0_spec;
wire iu_rv_iu6_t1_i0_t1_v;
wire [0:2] iu_rv_iu6_t1_i0_t1_t;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_p;
wire iu_rv_iu6_t1_i0_t2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_p;
wire [0:2] iu_rv_iu6_t1_i0_t2_t;
wire iu_rv_iu6_t1_i0_t3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_p;
wire [0:2] iu_rv_iu6_t1_i0_t3_t;
wire iu_rv_iu6_t1_i0_s1_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_p;
wire [0:2] iu_rv_iu6_t1_i0_s1_t;
wire iu_rv_iu6_t1_i0_s1_dep_hit;
wire iu_rv_iu6_t1_i0_s2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_p;
wire [0:2] iu_rv_iu6_t1_i0_s2_t;
wire iu_rv_iu6_t1_i0_s2_dep_hit;
wire iu_rv_iu6_t1_i0_s3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_p;
wire [0:2] iu_rv_iu6_t1_i0_s3_t;
wire iu_rv_iu6_t1_i0_s3_dep_hit;
wire [0:3] iu_rv_iu6_t1_i0_ilat;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_bta;
wire iu_rv_iu6_t1_i0_bta_val;
wire iu_rv_iu6_t1_i0_br_pred;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_fusion;
wire [0:2] iu_rv_iu6_t1_i0_ls_ptr;
wire [0:17] iu_rv_iu6_t1_i0_gshare;
wire iu_rv_iu6_t1_i0_bh_update;
wire iu_rv_iu6_t1_i0_isLoad;
wire iu_rv_iu6_t1_i0_isStore;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s3_itag;
wire iu_rv_iu6_t1_i1_vld;
wire iu_rv_iu6_t1_i1_act;
wire iu_rv_iu6_t1_i1_rte_lq;
wire iu_rv_iu6_t1_i1_rte_sq;
wire iu_rv_iu6_t1_i1_rte_fx0;
wire iu_rv_iu6_t1_i1_rte_fx1;
wire iu_rv_iu6_t1_i1_rte_axu0;
wire iu_rv_iu6_t1_i1_rte_axu1;
wire [0:31] iu_rv_iu6_t1_i1_instr;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_ifar;
wire [0:2] iu_rv_iu6_t1_i1_ucode;
wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i1_ucode_cnt;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_itag;
wire iu_rv_iu6_t1_i1_ord;
wire iu_rv_iu6_t1_i1_cord;
wire iu_rv_iu6_t1_i1_spec;
wire iu_rv_iu6_t1_i1_t1_v;
wire [0:2] iu_rv_iu6_t1_i1_t1_t;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_p;
wire iu_rv_iu6_t1_i1_t2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_p;
wire [0:2] iu_rv_iu6_t1_i1_t2_t;
wire iu_rv_iu6_t1_i1_t3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_p;
wire [0:2] iu_rv_iu6_t1_i1_t3_t;
wire iu_rv_iu6_t1_i1_s1_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_p;
wire [0:2] iu_rv_iu6_t1_i1_s1_t;
wire iu_rv_iu6_t1_i1_s2_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_p;
wire [0:2] iu_rv_iu6_t1_i1_s2_t;
wire iu_rv_iu6_t1_i1_s3_v;
wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p;
wire [0:2] iu_rv_iu6_t1_i1_s3_t;
wire [0:3] iu_rv_iu6_t1_i1_ilat;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_bta;
wire iu_rv_iu6_t1_i1_bta_val;
wire iu_rv_iu6_t1_i1_br_pred;
wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_fusion;
wire [0:2] iu_rv_iu6_t1_i1_ls_ptr;
wire [0:17] iu_rv_iu6_t1_i1_gshare;
wire iu_rv_iu6_t1_i1_bh_update;
wire iu_rv_iu6_t1_i1_isLoad;
wire iu_rv_iu6_t1_i1_isStore;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag;
`endif
// Credit Interface with IU
wire [0:`THREADS-1] rv_iu_fx0_credit_free;
wire [0:`THREADS-1] rv_iu_fx1_credit_free;
wire [0:`THREADS-1] rv_iu_axu0_credit_free;
wire [0:`THREADS-1] rv_iu_axu1_credit_free;
// LQ Instruction Executed
wire [0:`THREADS-1] lq0_iu_execute_vld;
wire [0:`ITAG_SIZE_ENC-1] lq0_iu_itag;
wire lq0_iu_n_flush;
wire lq0_iu_np1_flush;
wire lq0_iu_dacr_type;
wire [0:3] lq0_iu_dacrw;
wire [0:31] lq0_iu_instr;
wire [64-`GPR_WIDTH:63] lq0_iu_eff_addr;
wire lq0_iu_exception_val;
wire [0:5] lq0_iu_exception;
wire lq0_iu_flush2ucode;
wire lq0_iu_flush2ucode_type;
wire [0:`THREADS-1] lq0_iu_recirc_val;
wire [0:`THREADS-1] lq0_iu_dear_val;
wire [0:`THREADS-1] lq1_iu_execute_vld;
wire [0:`ITAG_SIZE_ENC-1] lq1_iu_itag;
wire lq1_iu_n_flush;
wire lq1_iu_np1_flush;
wire lq1_iu_exception_val;
wire [0:5] lq1_iu_exception;
wire lq1_iu_dacr_type;
wire [0:3] lq1_iu_dacrw;
wire [0:3] lq1_iu_perf_events;
wire [0:`THREADS-1] lq_iu_credit_free;
wire [0:`THREADS-1] sq_iu_credit_free;
wire pc_lq_init_reset;
// BR Instruction Executed
wire [0:`THREADS-1] br_iu_execute_vld;
wire [0:`ITAG_SIZE_ENC-1] br_iu_itag;
wire [62-`EFF_IFAR_ARCH:61] br_iu_bta;
wire br_iu_taken;
wire [0:`THREADS-1] br_iu_redirect;
wire [0:3] br_iu_perf_events;
//br unit repairs
wire [0:17] br_iu_gshare;
wire [0:2] br_iu_ls_ptr;
wire [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data;
wire br_iu_ls_update;
// AXU Instruction Executed
wire [0:`THREADS-1] axu0_rv_itag_vld;
wire [0:`ITAG_SIZE_ENC-1] axu0_rv_itag;
wire [0:`THREADS-1] axu1_rv_itag_vld;
wire [0:`ITAG_SIZE_ENC-1] axu1_rv_itag;
wire axu0_rv_hold_all;
wire axu1_rv_hold_all;
// Abort
wire lq_rv_ex2_s1_abort;
wire lq_rv_ex2_s2_abort;
wire fx0_rv_ex2_s1_abort;
wire fx0_rv_ex2_s2_abort;
wire fx0_rv_ex2_s3_abort;
wire fx1_rv_ex2_s1_abort;
wire fx1_rv_ex2_s2_abort;
wire fx1_rv_ex2_s3_abort;
wire axu0_rv_ex2_s1_abort;
wire axu0_rv_ex2_s2_abort;
wire axu0_rv_ex2_s3_abort;
wire fu_lq_ex3_abort;
// XU Instruction Executed
wire [0:`THREADS-1] xu_iu_ucode_xer_val;
wire [`XER_WIDTH-7:`XER_WIDTH-1] xu_iu_ucode_xer;
wire [0:`THREADS-1] xu_iu_execute_vld;
wire [0:`ITAG_SIZE_ENC-1] xu_iu_itag;
wire xu_iu_n_flush;
wire xu_iu_np1_flush;
wire xu_iu_flush2ucode;
wire [0:3] xu0_iu_perf_events;
wire xu_iu_exception_val;
wire [0:4] xu_iu_exception;
wire [0:`THREADS-1] xu_iu_mtiar;
wire [62-`EFF_IFAR_ARCH:61] xu_iu_bta;
wire [0:`THREADS-1] xu1_iu_execute_vld;
wire [0:`ITAG_SIZE_ENC-1] xu1_iu_itag;
wire [0:`THREADS-1] xu_iu_val;
wire [0:`THREADS-1] xu_iu_pri_val;
wire [0:2] xu_iu_pri;
wire xu_iu_is_eratre;
wire xu_iu_is_eratwe;
wire xu_iu_is_eratsx;
wire xu_iu_is_eratilx;
wire xu_iu_is_erativax;
wire [0:1] xu_iu_ws;
wire [0:2] xu_iu_t;
wire [0:8] xu_iu_rs_is; // Never see this used in IERAT
wire [0:3] xu_iu_ra_entry;
wire [64-`GPR_WIDTH:51] xu_iu_rb;
wire [64-`GPR_WIDTH:63] xu_iu_rs_data;
wire xu_iu_ord_ready;
wire iu_xu_ord_read_done;
wire iu_xu_ord_write_done;
wire iu_xu_ord_n_flush_req;
wire iu_xu_ord_par_err;
wire [0:`THREADS-1] mm_xu_ord_read_done;
wire [0:`THREADS-1] mm_xu_ord_write_done;
wire [0:`THREADS-1] mm_xu_ord_n_flush_req;
wire [0:`THREADS-1] mm_xu_ord_np1_flush_req;
wire mm_xu_ord_tlb_multihit;
wire mm_xu_ord_tlb_par_err;
wire mm_xu_ord_lru_par_err;
wire mm_xu_local_snoop_reject;
wire [0:`ITAG_SIZE_ENC-1] mm_xu_itag;
wire xu_mm_ord_ready;
wire [0:`THREADS-1] mm_xu_cr0_eq; // for record forms
wire [0:`THREADS-1] mm_xu_cr0_eq_valid; // for record forms
wire [0:`THREADS-1] mm_xu_tlb_miss;
wire [0:`THREADS-1] mm_xu_lrat_miss;
wire [0:`THREADS-1] mm_xu_tlb_inelig;
wire [0:`THREADS-1] mm_xu_pt_fault;
wire [0:`THREADS-1] mm_xu_hv_priv;
wire [0:`THREADS-1] mm_xu_illeg_instr;
wire [0:1] mm_xu_t0_mmucr0_tlbsel;
`ifndef THREADS1
wire [0:1] mm_xu_t1_mmucr0_tlbsel;
`endif
wire mm_xu_tlb_miss_ored;
wire mm_xu_lrat_miss_ored;
wire mm_xu_tlb_inelig_ored;
wire mm_xu_pt_fault_ored;
wire mm_xu_hv_priv_ored;
wire mm_xu_illeg_instr_ored;
wire mm_xu_cr0_eq_ored; // for record forms
wire mm_xu_cr0_eq_valid_ored; // for record forms
wire mm_xu_ord_n_flush_req_ored;
wire mm_xu_ord_np1_flush_req_ored;
wire mm_xu_ord_read_done_ored;
wire mm_xu_ord_write_done_ored;
wire mm_pc_tlb_multihit_err_ored;
wire mm_pc_tlb_par_err_ored;
wire mm_pc_lru_par_err_ored;
wire mm_pc_local_snoop_reject_ored;
wire [0:`THREADS-1] mm_tlb_multihit_err;
wire [0:`THREADS-1] mm_tlb_par_err;
wire [0:`THREADS-1] mm_lru_par_err;
wire [0:`THREADS-1] mm_iu_local_snoop_reject;
wire [64-`GPR_WIDTH:63] iu_xu_ex5_data;
wire xu_lq_act;
wire [0:`THREADS-1] xu_lq_val;
wire xu_lq_is_eratre;
wire xu_lq_is_eratwe;
wire xu_lq_is_eratsx;
wire xu_lq_is_eratilx;
wire [0:1] xu_lq_ws;
wire [0:2] xu_lq_t;
wire [0:8] xu_lq_rs_is; // Never see this used in IERAT
wire [0:4] xu_lq_ra_entry;
wire [64-`GPR_WIDTH:51] xu_lq_rb;
wire [64-`GPR_WIDTH:63] xu_lq_rs_data;
wire xu_lq_ord_ready;
wire xu_lq_hold_req;
wire lq_xu_ord_read_done;
wire lq_xu_ord_write_done;
wire lq_xu_ord_n_flush_req;
wire lq_xu_ord_par_err;
wire [64-`GPR_WIDTH:63] lq_xu_ex5_data;
wire lq_xu_dbell_val;
wire [0:4] lq_xu_dbell_type;
wire lq_xu_dbell_brdcast;
wire lq_xu_dbell_lpid_match;
wire [50:63] lq_xu_dbell_pirtag;
wire xu_mm_is_tlbre;
wire xu_mm_is_tlbwe;
wire xu_mm_is_tlbsx;
wire xu_mm_is_tlbsxr;
wire xu_mm_is_tlbsrx;
wire xu_mm_is_tlbivax;
wire xu_mm_is_tlbilx;
wire [0:11] xu_mm_ra_entry;
wire [64-`GPR_WIDTH:63] xu_mm_rb;
wire lq_xu_spr_xucr0_cslc_xuop;
wire lq_xu_spr_xucr0_cslc_binv;
wire lq_xu_spr_xucr0_clo;
wire lq_xu_spr_xucr0_cul;
wire [0:`THREADS-1] lq_iu_spr_dbcr3_ivc;
// FU Instruction Executed
wire [0:`THREADS-1] axu0_iu_execute_vld;
wire [0:`ITAG_SIZE_ENC-1] axu0_iu_itag;
wire axu0_iu_n_flush;
wire axu0_iu_np1_flush;
wire axu0_iu_n_np1_flush;
wire axu0_iu_flush2ucode;
wire axu0_iu_flush2ucode_type;
wire axu0_iu_exception_val;
wire [0:3] axu0_iu_exception;
wire [0:`THREADS-1] axu0_iu_async_fex;
wire [0:3] axu0_iu_perf_events;
wire [0:`THREADS-1] axu1_iu_execute_vld;
wire [0:`ITAG_SIZE_ENC-1] axu1_iu_itag;
wire axu1_iu_n_flush;
wire axu1_iu_np1_flush;
wire axu1_iu_flush2ucode;
wire axu1_iu_flush2ucode_type;
wire axu1_iu_exception_val;
wire [0:3] axu1_iu_exception;
wire [0:3] axu1_iu_perf_events;
wire [0:`THREADS-1] cp_flush;
wire [0:`ITAG_SIZE_ENC-1] cp_t0_next_itag;
wire [0:`ITAG_SIZE_ENC-1] cp_t0_flush_itag;
wire [62-`EFF_IFAR_ARCH:61] cp_t0_flush_ifar /* verilator public */;
2 years ago
wire [0:`THREADS-1] cp_axu_i0_t1_v;
wire [0:`THREADS-1] cp_axu_i1_t1_v;
wire [0:2] cp_axu_t0_i0_t1_t;
wire [0:`GPR_WIDTH_ENC-1] cp_axu_t0_i0_t1_p;
wire [0:2] cp_axu_t0_i1_t1_t;
wire [0:`GPR_WIDTH_ENC-1] cp_axu_t0_i1_t1_p;
wire [0:`ITAG_SIZE_ENC-1] cp_t1_next_itag;
wire [0:`ITAG_SIZE_ENC-1] cp_t1_flush_itag;
wire [62-`EFF_IFAR_ARCH:61] cp_t1_flush_ifar /* verilator public */;
2 years ago
wire [0:2] cp_axu_t1_i0_t1_t;
wire [0:`GPR_WIDTH_ENC-1] cp_axu_t1_i0_t1_p;
wire [0:2] cp_axu_t1_i1_t1_t;
wire [0:`GPR_WIDTH_ENC-1] cp_axu_t1_i1_t1_p;
wire cp_is_isync;
wire cp_is_csync;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu0_ex1_r0d;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu0_ex1_r1d;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu0_ex1_r2d;
wire xu0_gpr_ex6_we;
wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] xu0_gpr_ex6_wa;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] xu0_gpr_ex6_wd;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu1_ex1_r0d;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu1_ex1_r1d;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu1_ex1_r2d;
wire xu1_gpr_ex3_we;
wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] xu1_gpr_ex3_wd;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] rv_lq_gpr_ex1_r0d;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] rv_lq_gpr_ex1_r1d;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_lq_ex1_r2d;
wire lq_rv_gpr_ex6_we;
wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_ex6_wa;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] lq_rv_gpr_ex6_wd;
wire lq_xu_gpr_ex5_we;
wire [0:`AXU_SPARE_ENC+`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_ex5_wa;
wire lq_rv_gpr_rel_we;
wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_rel_wa;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] lq_rv_gpr_rel_wd;
wire lq_xu_gpr_rel_we;
wire [0:`AXU_SPARE_ENC+`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_rel_wa;
wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] lq_xu_gpr_rel_wd;
wire lq_xu_cr_ex5_we;
wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_ex5_wa;
wire lq_xu_cr_l2_we;
wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_l2_wa;
wire [0:3] lq_xu_cr_l2_wd;
wire [0:`XER_POOL_ENC-1] iu_rf_t0_xer_p;
`ifndef THREADS1
wire [0:`XER_POOL_ENC-1] iu_rf_t1_xer_p;
`endif
wire [0:`THREADS-1] xu_lq_xer_cp_rd;
// Interface to FX0
wire [0:`THREADS-1] rv_fx0_vld;
wire rv_fx0_s1_v;
wire [0:`GPR_POOL_ENC-1] rv_fx0_s1_p;
wire [0:2] rv_fx0_s1_t;
wire rv_fx0_s2_v;
wire [0:`GPR_POOL_ENC-1] rv_fx0_s2_p;
wire [0:2] rv_fx0_s2_t;
wire rv_fx0_s3_v;
wire [0:`GPR_POOL_ENC-1] rv_fx0_s3_p;
wire [0:2] rv_fx0_s3_t;
wire [0:31] rv_fx0_ex0_instr;
wire [62-`EFF_IFAR_WIDTH:61] rv_fx0_ex0_ifar;
wire [0:`ITAG_SIZE_ENC-1] rv_fx0_ex0_itag;
wire [0:2] rv_fx0_ex0_ucode;
wire [0:`UCODE_ENTRIES_ENC-1] rv_fx0_ex0_ucode_cnt;
wire rv_fx0_ex0_ord;
wire rv_fx0_ex0_t1_v;
wire [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t1_p;
wire [0:2] rv_fx0_ex0_t1_t;
wire rv_fx0_ex0_t2_v;
wire [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t2_p;
wire [0:2] rv_fx0_ex0_t2_t;
wire rv_fx0_ex0_t3_v;
wire [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t3_p;
wire [0:2] rv_fx0_ex0_t3_t;
wire rv_fx0_ex0_s1_v;
wire rv_fx0_ex0_s2_v;
wire [0:2] rv_fx0_ex0_s2_t;
wire rv_fx0_ex0_s3_v;
wire [0:2] rv_fx0_ex0_s3_t;
wire [0:19] rv_fx0_ex0_fusion;
wire [62-`EFF_IFAR_WIDTH:61] rv_fx0_ex0_pred_bta;
wire rv_fx0_ex0_bta_val;
wire rv_fx0_ex0_br_pred;
wire [0:2] rv_fx0_ex0_ls_ptr;
wire rv_fx0_ex0_bh_update;
wire [0:17] rv_fx0_ex0_gshare;
wire [0:`THREADS-1] rv_fx0_ex0_spec_flush;
wire [0:`THREADS-1] rv_fx0_ex1_spec_flush;
wire [0:`THREADS-1] rv_fx0_ex2_spec_flush;
wire fx0_rv_hold_all;
wire [0:`ITAG_SIZE_ENC-1] fx0_rv_ord_itag;
wire fx0_rv_ord_complete;
// Interface to FX1
wire [0:`THREADS-1] rv_fx1_vld;
wire rv_fx1_s1_v;
wire [0:`GPR_POOL_ENC-1] rv_fx1_s1_p;
wire [0:2] rv_fx1_s1_t;
wire rv_fx1_s2_v;
wire [0:`GPR_POOL_ENC-1] rv_fx1_s2_p;
wire [0:2] rv_fx1_s2_t;
wire rv_fx1_s3_v;
wire [0:`GPR_POOL_ENC-1] rv_fx1_s3_p;
wire [0:2] rv_fx1_s3_t;
wire [0:31] rv_fx1_ex0_instr;
wire [0:`ITAG_SIZE_ENC-1] rv_fx1_ex0_itag;
wire [0:2] rv_fx1_ex0_ucode;
wire rv_fx1_ex0_t1_v;
wire [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t1_p;
wire rv_fx1_ex0_t2_v;
wire [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t2_p;
wire rv_fx1_ex0_t3_v;
wire [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t3_p;
wire rv_fx1_ex0_s1_v;
wire [0:2] rv_fx1_ex0_s3_t;
wire rv_fx1_ex0_isStore;
wire [0:`THREADS-1] rv_fx1_ex0_spec_flush;
wire [0:`THREADS-1] rv_fx1_ex1_spec_flush;
wire [0:`THREADS-1] rv_fx1_ex2_spec_flush;
wire fx1_rv_hold_all;
wire fx1_rv_hold_ordered;
//------------------------------------------------------------------
// AXU Pass Thru Interface
//------------------------------------------------------------------
wire [59:63] lq_xu_axu_ex4_addr;
wire lq_xu_axu_ex5_we;
wire lq_xu_axu_ex5_le;
wire [59:63] xu_axu_lq_ex4_addr;
wire xu_axu_lq_ex5_we;
wire xu_axu_lq_ex5_le;
wire [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu_axu_lq_ex5_wa;
wire [(128-`STQ_DATA_SIZE):127] xu_axu_lq_ex5_wd;
wire lq_xu_axu_rel_we;
wire lq_xu_axu_rel_le;
wire xu_axu_lq_rel_we;
wire xu_axu_lq_rel_le;
wire [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu_axu_lq_rel_wa;
wire [(128-`STQ_DATA_SIZE):128+((`STQ_DATA_SIZE-1)/8)] xu_axu_lq_rel_wd;
wire [0:`THREADS-1] axu_xu_lq_ex_stq_val;
wire [0:`ITAG_SIZE_ENC-1] axu_xu_lq_ex_stq_itag;
wire [128-`STQ_DATA_SIZE:127] axu_xu_lq_exp1_stq_data;
wire [0:`THREADS-1] xu_lq_axu_ex_stq_val;
wire [0:`ITAG_SIZE_ENC-1] xu_lq_axu_ex_stq_itag;
wire [128-`STQ_DATA_SIZE:127] xu_lq_axu_exp1_stq_data;
wire axu_xu_lq_exp1_sto_parity_err;
// Interface to LQ
wire [0:`THREADS-1] rv_lq_rvs_empty;
wire [0:`THREADS-1] rv_lq_vld;
wire [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_itag;
wire rv_lq_isLoad;
wire [0:`THREADS-1] rv_lq_rv1_i0_vld;
wire rv_lq_rv1_i0_ucode_preissue;
wire rv_lq_rv1_i0_2ucode;
wire [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt;
wire [0:2] rv_lq_rv1_i0_s3_t;
wire rv_lq_rv1_i0_isLoad;
wire rv_lq_rv1_i0_isStore;
wire [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag;
wire rv_lq_rv1_i0_rte_lq;
wire rv_lq_rv1_i0_rte_sq;
wire [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i0_ifar;
wire [0:`THREADS-1] rv_lq_rv1_i1_vld;
wire rv_lq_rv1_i1_ucode_preissue;
wire rv_lq_rv1_i1_2ucode;
wire [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt;
wire [0:2] rv_lq_rv1_i1_s3_t;
wire rv_lq_rv1_i1_isLoad;
wire rv_lq_rv1_i1_isStore;
wire [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag;
wire rv_lq_rv1_i1_rte_lq;
wire rv_lq_rv1_i1_rte_sq;
wire [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i1_ifar;
wire [0:31] rv_lq_ex0_instr;
wire [0:2] rv_lq_ex0_ucode;
wire [0:`UCODE_ENTRIES_ENC-1] rv_lq_ex0_ucode_cnt;
wire rv_lq_ex0_spec;
wire rv_lq_ex0_t1_v;
wire [0:`GPR_POOL_ENC-1] rv_lq_ex0_t1_p;
wire [0:`GPR_POOL_ENC-1] rv_lq_ex0_t3_p;
wire rv_lq_ex0_s1_v;
wire rv_lq_ex0_s2_v;
wire [0:2] rv_lq_ex0_s2_t;
wire lq_rv_hold_all;
wire [0:`THREADS-1] lq_rv_itag0_vld;
wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag0;
wire [0:`THREADS-1] lq_rv_itag1_vld;
wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1;
wire [0:`THREADS-1] lq_rv_itag2_vld;
wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag2;
wire lq_rv_itag0_spec;
wire lq_rv_itag0_abort;
wire lq_rv_itag1_restart;
wire lq_rv_itag1_abort;
wire lq_rv_itag1_hold;
wire lq_rv_itag1_cord;
wire [0:`THREADS-1] lq_rv_clr_hold;
wire lq_rv_ord_complete;
wire [0:`GPR_POOL_ENC-1] rv_sq_s3_p;
wire [0:`THREADS-1] rv_axu0_vld;
wire rv_axu0_s1_v;
wire [0:`GPR_POOL_ENC-1] rv_axu0_s1_p;
wire [0:2] rv_axu0_s1_t;
wire rv_axu0_s2_v;
wire [0:`GPR_POOL_ENC-1] rv_axu0_s2_p;
wire [0:2] rv_axu0_s2_t;
wire rv_axu0_s3_v;
wire [0:`GPR_POOL_ENC-1] rv_axu0_s3_p;
wire [0:2] rv_axu0_s3_t;
wire rv_axu0_s1_spec;
wire [0:`ITAG_SIZE_ENC-1] rv_axu0_s1_itag;
wire rv_axu0_s2_spec;
wire [0:`ITAG_SIZE_ENC-1] rv_axu0_s2_itag;
wire rv_axu0_s3_spec;
wire [0:`ITAG_SIZE_ENC-1] rv_axu0_s3_itag;
wire [0:`ITAG_SIZE_ENC-1] rv_axu0_ex0_itag;
wire [0:31] rv_axu0_ex0_instr;
wire [0:2] rv_axu0_ex0_ucode;
wire rv_axu0_ex0_t1_v;
wire [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t1_p;
wire [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t2_p;
wire [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t3_p;
wire axu0_rv_ord_complete;
wire sq_rv_itag0_vld;
wire [0:`ITAG_SIZE_ENC-1] sq_rv_itag0;
wire [0:`THREADS-1] iu_lq_i0_completed;
wire [0:`THREADS-1] iu_lq_i1_completed;
wire [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i0_completed_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i1_completed_itag;
`ifndef THREADS1
wire [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i0_completed_itag;
wire [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i1_completed_itag;
`endif
wire [0:`THREADS-1] iu_lq_recirc_val;
wire [64-(2**`GPR_WIDTH_ENC):63] iu_lq_ls5_tlb_data;
wire [0:`THREADS-1] fu_lq_ex2_store_data_val;
wire [0:`ITAG_SIZE_ENC-1] fu_lq_ex2_store_itag;
wire [(128-`STQ_DATA_SIZE):127] fu_lq_ex3_store_data;
wire [0:`THREADS-1] mm_lq_lsu_req;
wire [0:1] mm_lq_lsu_ttype;
wire [0:4] mm_lq_lsu_wimge;
wire [0:3] mm_lq_lsu_u;
wire [64-`REAL_IFAR_WIDTH:63] mm_lq_lsu_addr;
wire [0:7] mm_lq_lsu_lpid;
wire [0:7] mm_lq_lsu_lpidr;
wire mm_lq_lsu_gs;
wire mm_lq_lsu_ind;
wire mm_lq_lsu_lbit;
wire lq_mm_lsu_token;
wire xu_lq_xucr0_aflsta;
wire xu_lq_xucr0_cred;
wire xu_lq_xucr0_rel;
wire xu_lq_xucr0_flsta;
wire xu_lq_xucr0_l2siw;
wire xu_lq_xucr0_flh2l2;
wire xu_lq_xucr0_dc_dis;
wire xu_lq_xucr0_wlk;
wire xu_lq_xucr0_clfc;
wire xu_lq_xucr0_bypErat;
wire lq_mm_derat_req;
wire [0:51] lq_mm_derat_epn;
wire [0:`THREADS-1] lq_mm_derat_thdid;
wire [0:`EMQ_ENTRIES-1] lq_mm_derat_req_emq;
wire [0:1] lq_mm_derat_ttype;
wire [0:3] lq_mm_derat_state;
wire [0:7] lq_mm_derat_lpid;
wire [0:13] lq_mm_derat_tid;
wire lq_mm_derat_req_nonspec;
wire [0:`ITAG_SIZE_ENC-1] lq_mm_derat_req_itag;
wire [0:`THREADS-1] lq_mm_perf_dtlb;
wire [0:4] mm_lq_derat_rel_val;
wire [0:131] mm_lq_derat_rel_data;
wire [0:`EMQ_ENTRIES-1] mm_lq_derat_rel_emq;
wire [0:`ITAG_SIZE_ENC-1] mm_lq_derat_rel_itag;
wire mm_lq_derat_snoop_coming;
wire mm_lq_derat_snoop_val;
wire [0:25] mm_lq_derat_snoop_attr;
wire [(62-`EFF_IFAR_ARCH):51] mm_lq_derat_snoop_vpn;
wire lq_mm_derat_snoop_ack;
wire [0:13] mm_lq_t0_derat_pid;
wire [0:19] mm_lq_t0_derat_mmucr0;
`ifndef THREADS1
wire [0:13] mm_lq_t1_derat_pid;
wire [0:19] mm_lq_t1_derat_mmucr0;
`endif
wire [0:17] lq_mm_derat_mmucr0;
wire [0:`THREADS-1] lq_mm_derat_mmucr0_we;
wire [0:9] mm_lq_derat_mmucr1;
wire [0:4] lq_mm_derat_mmucr1;
wire [0:`THREADS-1] lq_mm_derat_mmucr1_we;
wire lq_mm_lmq_stq_empty;
// Interface to BR
// Interface to AXU
wire [59:63] lq_fu_ex4_eff_addr;
wire lq_fu_ex5_load_val;
wire lq_fu_ex5_load_le;
wire [(128-`STQ_DATA_SIZE):127] lq_fu_ex5_load_data;
// Ram interface
wire [0:31] pc_iu_ram_instr;
wire [0:3] pc_iu_ram_instr_ext;
wire [0:`THREADS-1] pc_iu_ram_active;
wire [0:`THREADS-1] pc_iu_ram_flush_thread;
wire pc_iu_ram_issue;
wire iu_pc_ram_done;
wire iu_pc_ram_interrupt;
wire iu_pc_ram_unsupported;
wire xu_pc_ram_data_val;
wire [64-(2**`GPR_WIDTH_ENC):63] xu_pc_ram_data;
wire xu_pc_ram_exception;
wire [0:`THREADS-1] pc_xu_ram_active;
wire pc_xu_msrovride_enab;
wire [0:`THREADS-1] xu_iu_msrovride_enab;
wire pc_xu_msrovride_pr;
wire pc_xu_msrovride_gs;
wire pc_xu_msrovride_de;
wire [0:`THREADS-1] pc_lq_ram_active;
wire lq_pc_ram_data_val;
wire [64-(2**`GPR_WIDTH_ENC):63] lq_pc_ram_data;
// PC control
wire [0:`THREADS-1] pc_iu_stop;
wire [0:`THREADS-1] pc_iu_step;
wire [0:`THREADS-1] iu_pc_step_done;
wire [0:`THREADS-1] iu_pc_stop_dbg_event;
wire [0:`THREADS-1] xu_pc_stop_dnh_instr;
wire [0:2] pc_iu_t0_dbg_action;
`ifndef THREADS1
wire [0:2] pc_iu_t1_dbg_action;
`endif
wire [0:3*`THREADS-1] pc_iu_dbg_action_int;
wire pc_xu_extirpts_dis_on_stop;
wire pc_xu_timebase_dis_on_stop;
wire pc_xu_decrem_dis_on_stop;
wire ac_an_power_managed_int;
wire [0:`THREADS-1] pc_xu_spr_dbcr0_edm;
wire [0:`THREADS-1] pc_iu_spr_dbcr0_edm;
// MSR connections
wire [0:`THREADS-1] spr_msr_ucle;
wire [0:`THREADS-1] spr_msr_spv;
wire [0:`THREADS-1] spr_msr_fp;
wire [0:`THREADS-1] spr_msr_fe0;
wire [0:`THREADS-1] spr_msr_fe1;
wire [0:`THREADS-1] spr_msr_de;
wire [0:`THREADS-1] spr_msrp_uclep;
wire [0:`THREADS-1] spr_msr_pr;