add source

rel/build/a2x/a2x_impl_step.tcl

@@ -0,0 +1,20 @@
+#synth_design -top a2x_axi_bd_wrapper -part xcvu3p-ffvc1517-2-e -verbose
+#source ila_axi.tcl
+set version v0
+
+write_checkpoint -force a2x_axi_synth_${version}.dcp
+
+opt_design -retarget -propconst -bram_power_opt 
+place_design -directive Explore
+phys_opt_design -directive Explore
+route_design -directive Explore
+phys_opt_design -directive Explore
+write_checkpoint -force a2x_axi_routed_${version}.dcp 
+
+report_utilization -file  utilization_route_design_${version}.rpt
+report_timing_summary -max_paths 100 -file timing_routed_summary_${version}.rpt
+
+write_bitstream -force -bin_file a2x_axi_${version}
+write_debug_probes -force a2x_axi_${version}
+write_cfgmem -force -format BIN -interface SPIx8 -size 256 -loadbit "up 0 a2x_axi_${version}.bit" a2x_axi_${version}
+

rel/build/a2x/bd/hdl/a2x_axi_bd_wrapper.v

@@ -0,0 +1,24 @@
+//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2019.1.3_CR1055600 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+//Date        : Wed Apr  8 10:49:50 2020
+//Host        : apdegl15aa.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.5 (Maipo)
+//Command     : generate_target a2x_axi_bd_wrapper.bd
+//Design      : a2x_axi_bd_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module a2x_axi_bd_wrapper
+   (clk_in1_n_0,
+    clk_in1_p_0);
+  input clk_in1_n_0;
+  input clk_in1_p_0;
+
+  wire clk_in1_n_0;
+  wire clk_in1_p_0;
+
+  a2x_axi_bd a2x_axi_bd_i
+       (.clk_in1_n_0(clk_in1_n_0),
+        .clk_in1_p_0(clk_in1_p_0));
+endmodule

rel/build/a2x/fixup_a2x_bd.tcl

@@ -0,0 +1,50 @@
+open_bd_design "[get_property DIRECTORY [current_project]]/proj_a2x_axi.srcs/sources_1/bd/a2x_axi_bd/a2x_axi_bd.bd"
+
+set_property SCREENSIZE {1 1} [get_bd_cells /pain]
+set_property location {5 1506 2372} [get_bd_cells pain]
+set_property SCREENSIZE {1 1} [get_bd_cells /thold_0]
+set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_0]
+set_property location {6 2778 2069} [get_bd_cells xlconstant_0]
+set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_1]
+set_property location {6 2734 2210} [get_bd_cells xlconstant_1]
+
+# so xil actually connects as bus
+set_property SCREENSIZE {1 1} [get_bd_cells /mchk_rv]
+set_property location {6 2767 2847} [get_bd_cells mchk_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /rcov_rv]
+set_property location {6 2777 2748} [get_bd_cells rcov_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /checkstop_rv]
+set_property location {7 2850 2630} [get_bd_cells rcov_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /scomdata_rv]
+set_property location {4 1355 2564} [get_bd_cells scomdata_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /thread_running_rv]
+set_property location {5 2152 2682} [get_bd_cells thread_running_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /axi_reg00_rv]
+set_property location {7 3176 2490} [get_bd_cells axi_reg00_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /reverserator_4_0]
+set_property location {7 2156 2797} [get_bd_cells reverserator_4_0]
+
+
+
+set_property SCREENSIZE {600 600} [get_bd_cells /a2x_axi_1]
+set_property location {5 2000 1000} [get_bd_cells /a2x_axi_1]
+set_property location {4 1306 1980} [get_bd_cells a2x_dbug]
+
+set_property location {4.5 1482 792} [get_bd_cells jtag_axi_0]
+
+set_property location {4 1259 2326} [get_bd_cells vio_dbug] ;# no orientation, highlight, etc.
+set_property location {5 1957 2377} [get_bd_cells vio_ctrl]
+set_property location {6 2704 2401} [get_bd_cells vio_terror]
+set_property location {7 3253 2629} [get_bd_cells vio_reg]
+
+set_property location {10.5 4307 861} [get_bd_cells blk_mem_gen_1]
+set_property location {11 4297 974} [get_bd_cells blk_mem_gen_2]
+
+set_property location {6 2034 684} [get_bd_cells axi_smc]
+
+set_property location {7 3129 422} [get_bd_cells ila_axi]
+set_property location {9 3542 548} [get_bd_cells ila_axi_protocol]
+set_property location {7 3173 580} [get_bd_cells axi_protocol_checker]
+
+save_bd_design
+

rel/build/a2x/readme.md

@@ -0,0 +1,31 @@
+# create/build project
+
+```
+$VIVADO -mode tcl -source create_a2x_project.tcl
+
+$VIVADO proj/proj_a2x_axi.xpr
+
+source ./fixup_a2x_bd.tcl
+
+>run synthesis (synth_2)
+>open synthesized design
+
+source ./ila_axi.tcl
+>set up debug 
+>   all clk
+>   8192/3 
+
+source ./a2x_impl_step.tcl
+```
+
+```
+a2x_axi_routed_v0.dcp
+a2x_axi_synth_v0.dcp
+a2x_axi_v0.bin
+a2x_axi_v0.bit
+a2x_axi_v0.ltx
+a2x_axi_v0_primary.bin
+a2x_axi_v0_primary.prm
+a2x_axi_v0_secondary.bin
+a2x_axi_v0_secondary.prm
+```

rel/build/a2x/xdc

@@ -0,0 +1 @@
+../xdc

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux16.vhdl

@@ -0,0 +1,154 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support; use support.power_logic_pkg.all;
+
+entity c_debug_mux16 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group4         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group5         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group6         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group7         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group8         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group9         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group10        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group11        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group12        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group13        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group14        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group15        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux16;
+
+
+architecture c_debug_mux16 of c_debug_mux16 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+signal unused                   : std_ulogic;
+
+begin
+
+    unused <= select_bits(4);
+
+    with select_bits(0 to 3) select debug_grp_selected <= 
+      dbg_group0    when "0000",
+      dbg_group1    when "0001",
+      dbg_group2    when "0010",
+      dbg_group3    when "0011",
+      dbg_group4    when "0100",
+      dbg_group5    when "0101",
+      dbg_group6    when "0110",
+      dbg_group7    when "0111",
+      dbg_group8    when "1000",
+      dbg_group9    when "1001",
+      dbg_group10   when "1010",
+      dbg_group11   when "1011",
+      dbg_group12   when "1100",
+      dbg_group13   when "1101",
+      dbg_group14   when "1110",
+      dbg_group15   when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux16;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux32.vhdl

@@ -0,0 +1,184 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support;
+use support.power_logic_pkg.all;
+
+entity c_debug_mux32 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group4         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group5         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group6         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group7         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group8         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group9         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group10        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group11        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group12        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group13        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group14        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group15        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group16        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group17        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group18        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group19        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group20        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group21        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group22        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group23        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group24        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group25        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group26        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group27        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group28        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group29        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group30        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group31        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux32;
+
+
+architecture c_debug_mux32 of c_debug_mux32 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+begin
+
+
+    with select_bits(0 to 4) select debug_grp_selected <= 
+      dbg_group0    when "00000",
+      dbg_group1    when "00001",
+      dbg_group2    when "00010",
+      dbg_group3    when "00011",
+      dbg_group4    when "00100",
+      dbg_group5    when "00101",
+      dbg_group6    when "00110",
+      dbg_group7    when "00111",
+      dbg_group8    when "01000",
+      dbg_group9    when "01001",
+      dbg_group10   when "01010",
+      dbg_group11   when "01011",
+      dbg_group12   when "01100",
+      dbg_group13   when "01101",
+      dbg_group14   when "01110",
+      dbg_group15   when "01111",
+      dbg_group16   when "10000",
+      dbg_group17   when "10001",
+      dbg_group18   when "10010",
+      dbg_group19   when "10011",
+      dbg_group20   when "10100",
+      dbg_group21   when "10101",
+      dbg_group22   when "10110",
+      dbg_group23   when "10111",
+      dbg_group24   when "11000",
+      dbg_group25   when "11001",
+      dbg_group26   when "11010",
+      dbg_group27   when "11011",
+      dbg_group28   when "11100",
+      dbg_group29   when "11101",
+      dbg_group30   when "11110",
+      dbg_group31   when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux32;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux4.vhdl

@@ -0,0 +1,131 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support;
+use support.power_logic_pkg.all;
+
+entity c_debug_mux4 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux4;
+
+
+architecture c_debug_mux4 of c_debug_mux4 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+signal unused                   : std_ulogic;
+
+begin
+
+    unused <= select_bits(2) or select_bits(3) or select_bits(4);
+
+    with select_bits(0 to 1) select debug_grp_selected <= 
+      dbg_group0    when "00",
+      dbg_group1    when "01",
+      dbg_group2    when "10",
+      dbg_group3    when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux4;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux8.vhdl

@@ -0,0 +1,139 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support;
+use support.power_logic_pkg.all;
+
+entity c_debug_mux8 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group4         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group5         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group6         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group7         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux8;
+
+
+architecture c_debug_mux8 of c_debug_mux8 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+signal unused                   : std_ulogic;
+
+begin
+
+    unused <= select_bits(3) or select_bits(4);
+
+    with select_bits(0 to 2) select debug_grp_selected <= 
+      dbg_group0    when "000",
+      dbg_group1    when "001",
+      dbg_group2    when "010",
+      dbg_group3    when "011",
+      dbg_group4    when "100",
+      dbg_group5    when "101",
+      dbg_group6    when "110",
+      dbg_group7    when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux8;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_event_mux.vhdl

@@ -0,0 +1,146 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,support,ibm;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+
+entity c_event_mux is
+  generic( events_in      : integer := 32;  
+           events_out     : integer := 8 ); 
+  port(
+     vd             : inout power_logic;
+     gd             : inout power_logic;
+     t0_events      : in  std_ulogic_vector(0 to events_in/4-1);
+     t1_events      : in  std_ulogic_vector(0 to events_in/4-1);
+     t2_events      : in  std_ulogic_vector(0 to events_in/4-1);
+     t3_events      : in  std_ulogic_vector(0 to events_in/4-1);
+
+     select_bits    : in  std_ulogic_vector(0 to ((events_in/64+4)*events_out)-1);
+
+     event_bits     : out std_ulogic_vector(0 to events_out-1)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_event_mux;
+
+
+architecture c_event_mux of c_event_mux is
+
+  constant INCR                 : natural := events_in/64+4;    
+  constant SIZE                 : natural := events_in/64+1;    
+
+
+  signal inMuxDec               : std_ulogic_vector(0 to events_out*events_in/4-1);
+  signal inMuxOut               : std_ulogic_vector(0 to events_out*events_in/4-1);
+
+  signal thrd_sel               : std_ulogic_vector(0 to events_out-1);
+  signal inMux_sel              : std_ulogic_vector(0 to ((events_in/64+3)*events_out)-1);
+
+
+begin
+  thrd_sel    <= select_bits(0*INCR) & select_bits(1*INCR) &
+                 select_bits(2*INCR) & select_bits(3*INCR) &
+                 select_bits(4*INCR) & select_bits(5*INCR) &
+                 select_bits(6*INCR) & select_bits(7*INCR) ;
+
+  inMux_sel   <= select_bits(0*INCR+1 to (0+1)*INCR-1) &
+                 select_bits(1*INCR+1 to (1+1)*INCR-1) &
+                 select_bits(2*INCR+1 to (2+1)*INCR-1) &
+                 select_bits(3*INCR+1 to (3+1)*INCR-1) &
+                 select_bits(4*INCR+1 to (4+1)*INCR-1) &
+                 select_bits(5*INCR+1 to (5+1)*INCR-1) &
+                 select_bits(6*INCR+1 to (6+1)*INCR-1) &
+                 select_bits(7*INCR+1 to (7+1)*INCR-1) ;
+
+
+  decode: for X in 0 to events_out-1 generate
+    Mux32: if (events_in = 32) generate
+        inMuxDec(X*events_in/4 to X*events_in/4+7)  <= decode_3to8(inMux_sel(X*3 to X*3+2));
+    end generate Mux32;
+
+    Mux64: if (events_in = 64) generate
+        inMuxDec(X*events_in/4 to X*events_in/4+15) <= decode_4to16(inMux_sel(X*4 to X*4+3));
+    end generate Mux64;
+
+    Mux128: if (events_in = 128) generate
+        inMuxDec(X*events_in/4 to X*events_in/4+31) <= decode_5to32(inMux_sel(X*5 to X*5+4));
+    end generate Mux128;
+  end generate decode;
+
+
+  inpMuxHi: for X in 0 to events_out/2-1 generate
+      eventSel: for I in 0 to events_in/4-1 generate
+          inMuxOut(X*events_in/4 + I) <=
+              ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t0_events(I)) or  
+               (inMuxDec(X*events_in/4 + I) and     thrd_sel(X) and t1_events(I)) );  
+      end generate eventSel;
+  end generate inpMuxHi;
+
+  inpMuxLo: for X in events_out/2 to events_out-1 generate
+      eventSel: for I in 0 to events_in/4-1 generate
+          inMuxOut(X*events_in/4 + I) <=
+              ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t2_events(I)) or  
+               (inMuxDec(X*events_in/4 + I) and     thrd_sel(X) and t3_events(I)) ); 
+      end generate eventSel;
+  end generate inpMuxLo;
+
+
+  bitOutHi: for X in 0 to events_out/2-1 generate
+    Mux32: if (events_in = 32) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
+    end generate Mux32;
+
+    Mux64: if (events_in = 64) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
+    end generate Mux64;
+
+    Mux128: if (events_in = 128) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
+    end generate Mux128;
+  end generate bitOutHi;
+
+  bitOutLo: for X in events_out/2 to events_out-1 generate
+    Mux32: if (events_in = 32) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
+    end generate Mux32;
+
+    Mux64: if (events_in = 64) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
+    end generate Mux64;
+
+    Mux128: if (events_in = 128) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
+    end generate Mux128;
+  end generate bitOutLo;
+
+end c_event_mux;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_bthmx.vhdl

@@ -0,0 +1,97 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm;
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+library support; use support.power_logic_pkg.all;
+
+ENTITY c_prism_bthmx IS
+    GENERIC ( btr : string := "BTHMX_X1_A12TH"  );
+    PORT(
+     X      : IN  STD_ULOGIC;
+     SNEG   : IN  STD_ULOGIC; 
+     SX     : IN  STD_ULOGIC; 
+     SX2    : IN  STD_ULOGIC; 
+     RIGHT  : IN  STD_ULOGIC; 
+     LEFT   : OUT STD_ULOGIC; 
+     Q      : OUT STD_ULOGIC; 
+     vd     : inout power_logic;
+     gd     : inout power_logic
+  );
+
+-- synopsys translate_off
+
+
+    ATTRIBUTE PIN_BIT_INFORMATION of c_prism_bthmx : entity is
+      (
+        1 => ("   ","X       ","SAME","PIN_BIT_SCALAR"),
+        2 => ("   ","SNEG    ","SAME","PIN_BIT_SCALAR"),
+        3 => ("   ","SX      ","SAME","PIN_BIT_SCALAR"),
+        4 => ("   ","SX2     ","SAME","PIN_BIT_SCALAR"),
+        5 => ("   ","RIGHT   ","SAME","PIN_BIT_SCALAR"),
+        6 => ("   ","LEFT    ","SAME","PIN_BIT_SCALAR"),
+        7 => ("   ","Q       ","SAME","PIN_BIT_SCALAR"),
+        8 => ("   ","VDD     ","SAME","PIN_BIT_SCALAR"),
+        9 => ("   ","VSS     ","SAME","PIN_BIT_SCALAR")
+        );
+-- synopsys translate_on
+END                               c_prism_bthmx;
+
+ARCHITECTURE c_prism_bthmx OF c_prism_bthmx IS
+
+   SIGNAL CENTER :STD_ULOGIC;
+   SIGNAL XN     :STD_ULOGIC;
+   SIGNAL SPOS   :STD_ULOGIC;
+
+
+BEGIN
+
+   XN <= NOT X;
+
+   SPOS <= NOT SNEG;
+
+   CENTER <= NOT( ( XN AND SPOS ) OR 
+                  ( X  AND SNEG )   );
+
+   LEFT <= CENTER; 
+
+
+   Q <= ( CENTER AND  SX  ) OR 
+        ( RIGHT  AND  SX2 ) ;
+
+
+END;
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa32.vhdl

@@ -0,0 +1,82 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm;
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+library support; use support.power_logic_pkg.all;
+
+ENTITY c_prism_csa32 IS
+   GENERIC ( btr : string := "CSA32_A2_A12TH" );
+   PORT(
+   A       : IN  std_ulogic;
+   B       : IN  std_ulogic;
+   C       : IN  std_ulogic;
+   CAR     : OUT std_ulogic;
+   SUM     : OUT std_ulogic;
+   vd      : inout power_logic;
+   gd      : inout power_logic
+  );
+
+-- synopsys translate_off
+
+
+   ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa32 : entity is
+     (
+       1 => ("   ","A       ","SAME","PIN_BIT_SCALAR"),
+       2 => ("   ","B       ","SAME","PIN_BIT_SCALAR"),
+       3 => ("   ","C       ","SAME","PIN_BIT_SCALAR"),
+       4 => ("   ","CAR     ","SAME","PIN_BIT_SCALAR"),
+       5 => ("   ","SUM     ","SAME","PIN_BIT_SCALAR"),
+       6 => ("   ","VDD     ","SAME","PIN_BIT_SCALAR"),
+       7 => ("   ","VSS     ","SAME","PIN_BIT_SCALAR")
+       );
+-- synopsys translate_on
+END                               c_prism_csa32;
+
+ARCHITECTURE c_prism_csa32 OF c_prism_csa32 IS
+
+
+BEGIN
+
+  sum <= a  XOR b  XOR c ;
+
+  car <= (a  AND b ) OR
+         (a  AND c ) OR
+         (b  AND c );
+
+
+END;
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa42.vhdl

@@ -0,0 +1,96 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ; 
+library support;
+library ibm;
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+  use support.power_logic_pkg.all;
+
+ENTITY c_prism_csa42 IS
+  GENERIC ( btr : string := "CSA42_A2_A12TH" );
+  PORT( 
+   A       : IN  std_ulogic;
+   B       : IN  std_ulogic;
+   C       : IN  std_ulogic;
+   D       : IN  std_ulogic;
+   KI      : IN  std_ulogic;
+   KO      : OUT std_ulogic;
+   CAR     : OUT std_ulogic;
+   SUM     : OUT std_ulogic;
+   vd      : inout power_logic;
+   gd      : inout power_logic
+  );
+
+-- synopsys translate_off
+
+
+   ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa42 : entity is
+     (
+       1  => ("   ","A       ","SAME","PIN_BIT_SCALAR"),
+       2  => ("   ","B       ","SAME","PIN_BIT_SCALAR"),
+       3  => ("   ","C       ","SAME","PIN_BIT_SCALAR"),
+       4  => ("   ","D       ","SAME","PIN_BIT_SCALAR"),
+       5  => ("   ","KI      ","SAME","PIN_BIT_SCALAR"),
+       6  => ("   ","KO      ","SAME","PIN_BIT_SCALAR"),
+       7  => ("   ","CAR     ","SAME","PIN_BIT_SCALAR"),
+       8  => ("   ","SUM     ","SAME","PIN_BIT_SCALAR"),
+       9  => ("   ","VDD     ","SAME","PIN_BIT_SCALAR"),
+       10 => ("   ","VSS     ","SAME","PIN_BIT_SCALAR")
+       );
+-- synopsys translate_on
+END                              c_prism_csa42;
+
+ARCHITECTURE c_prism_csa42 OF c_prism_csa42 IS
+
+ signal s1 : std_ulogic;
+
+BEGIN
+
+  s1    <= b  XOR c  XOR d ;
+  sum   <= s1 XOR a  XOR ki;
+
+  car   <= (s1 AND a ) OR
+           (s1 AND ki) OR
+           (a  AND ki);
+
+  ko   <= (b  AND c ) OR
+          (b  AND d ) OR
+          (c  AND d );
+
+
+END;
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_scom_addr_decode.vhdl

@@ -0,0 +1,70 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+library ieee,ibm,latches,clib, support;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+
+entity c_scom_addr_decode is
+   generic( satid_nobits  : positive := 5        
+          ; use_addr           : std_ulogic_vector := "1"
+          ; addr_is_rdable     : std_ulogic_vector := "1"
+          ; addr_is_wrable     : std_ulogic_vector := "1"
+          );
+   port( sc_addr     : in  std_ulogic_vector(0 to 11-satid_nobits-1) 
+       ; scaddr_dec  : out std_ulogic_vector(0 to use_addr'length-1) 
+       ; sc_req      : in  std_ulogic                                
+       ; sc_r_nw     : in  std_ulogic                                
+       ; scaddr_nvld : out std_ulogic                                
+       ; sc_wr_nvld  : out std_ulogic                                
+       ; sc_rd_nvld  : out std_ulogic                                
+       ; vd : inout power_logic
+       ; gd : inout power_logic
+       );
+
+end c_scom_addr_decode;
+
+
+
+architecture c_scom_addr_decode of c_scom_addr_decode is
+   signal address : std_ulogic_vector(0 to use_addr'length-1);
+begin
+   decode_it : for i in 0 to use_addr'length-1 generate
+      address(i) <= ((sc_addr = tconv(i,sc_addr'length)) and (use_addr(i)='1'));
+   end generate decode_it;
+
+   scaddr_dec  <= address;
+   scaddr_nvld <= sc_req and not or_reduce(address);
+   sc_wr_nvld  <= not or_reduce(address and addr_is_wrable) and sc_req and not sc_r_nw;
+   sc_rd_nvld  <= not or_reduce(address and addr_is_rdable) and sc_req and     sc_r_nw;
+end c_scom_addr_decode;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_unsigned.vhdl

@@ -0,0 +1,374 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+--***************************************************************************
+-- Copyright 2020 International Business Machines
+--
+-- Licensed under the Apache License, Version 2.0 (the “License”);
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- The patent license granted to you in Section 3 of the License, as applied
+-- to the “Work,” hereby includes implementations of the Work in physical form.
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an “AS IS” BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+--***************************************************************************
+library IEEE, IBM;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IBM.std_ulogic_support.all;
+
+package std_ulogic_unsigned is
+
+    function "+"(l: std_ulogic_vector; 	r: std_ulogic_vector) return std_ulogic_vector;
+    function "+"(l: std_ulogic_vector; 	r: integer)          return std_ulogic_vector;
+    function "+"(l: integer; 		r: std_ulogic_vector) return std_ulogic_vector;
+    function "+"(l: std_ulogic_vector;	r: std_ulogic)        return std_ulogic_vector;
+    function "+"(l: std_ulogic; 		r: std_ulogic_vector) return std_ulogic_vector;
+
+    function "-"(l: std_ulogic_vector; 	r: std_ulogic_vector) return std_ulogic_vector;
+    function "-"(l: std_ulogic_vector; 	r: integer)          return std_ulogic_vector;
+    function "-"(l: integer; 		r: std_ulogic_vector) return std_ulogic_vector;
+    function "-"(l: std_ulogic_vector; 	r: std_ulogic)        return std_ulogic_vector;
+    function "-"(l: std_ulogic; 		r: std_ulogic_vector) return std_ulogic_vector;
+
+    function "+"(l: std_ulogic_vector)                        return std_ulogic_vector;
+
+    function "*"(l: std_ulogic_vector; 	r: std_ulogic_vector) return std_ulogic_vector;
+
+  function "=" ( l : natural;          r : std_ulogic_vector) return boolean;
+  function "/="( l : natural;          r : std_ulogic_vector) return boolean;
+  function "<" ( l : natural;          r : std_ulogic_vector) return boolean;
+  function "<="( l : natural;          r : std_ulogic_vector) return boolean;
+  function ">" ( l : natural;          r : std_ulogic_vector) return boolean;
+  function ">="( l : natural;          r : std_ulogic_vector) return boolean;
+
+  function "=" ( l : std_ulogic_vector; r : natural)          return boolean;
+  function "/="( l : std_ulogic_vector; r : natural)          return boolean;
+  function "<" ( l : std_ulogic_vector; r : natural)          return boolean;
+  function "<="( l : std_ulogic_vector; r : natural)          return boolean;
+  function ">" ( l : std_ulogic_vector; r : natural)          return boolean;
+  function ">="( l : std_ulogic_vector; r : natural)          return boolean;
+  
+  function "=" ( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function "/="( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function "<" ( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function "<="( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function ">" ( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function ">="( l : natural;          r : std_ulogic_vector) return std_ulogic;
+
+  function "=" ( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function "/="( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function "<" ( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function "<="( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function ">" ( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function ">="( l : std_ulogic_vector; r : natural)          return std_ulogic;
+
+  function to_integer( d : std_ulogic_vector ) return natural;
+  -- synopsys translate_off
+  attribute type_convert        of to_integer : function is true;
+  attribute btr_name            of to_integer : function is "PASS";
+  attribute pin_bit_information of to_integer : function is
+           (1 => ("   ","A0      ","INCR","PIN_BIT_SCALAR"),
+            2 => ("   ","10      ","INCR","PIN_BIT_SCALAR"));
+  -- synopsys translate_on
+  
+  -- synopsys translate_off
+  function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector;
+  attribute type_convert        of to_std_ulogic_vector : function is true;
+  attribute btr_name            of to_std_ulogic_vector : function is "PASS";
+  attribute pin_bit_information of to_std_ulogic_vector : function is
+           (1 => ("   ","A0      ","INCR","PIN_BIT_SCALAR"),
+            2 => ("   ","10      ","INCR","PIN_BIT_SCALAR"));
+  -- synopsys translate_on
+  
+end std_ulogic_unsigned;
+
+package body std_ulogic_unsigned is
+
+    function maximum(L, R: INTEGER) return INTEGER is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        constant length : INTEGER := maximum(L'length, R'length);
+        variable result : UNSIGNED(length-1 downto 0);
+        -- pragma label_applies_to plus
+    begin
+        result  := UNSIGNED(L) + UNSIGNED(R);  -- pragma label plus
+        return   std_ulogic_vector(result);
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is
+       variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to plus
+    begin
+        result := std_ulogic_vector( UNSIGNED(L) + R ); -- pragma label plus
+        return  result ;
+    end;
+
+    function "+"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to plus
+    begin
+        result := std_ulogic_vector( L + UNSIGNED(R) ); -- pragma label plus
+        return  result;
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to plus
+    begin
+        if R = '1' then
+           result := std_ulogic_vector( UNSIGNED(L) + 1 );
+        else
+           result := L;
+        end if; 
+        return result ;
+    end;
+
+    function "+"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to plus
+    begin
+        if L = '1' then
+           result := std_ulogic_vector( UNSIGNED(R) + 1 );
+        else
+           result := R;
+        end if; 
+        return result ;
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to plus
+    begin
+        result := L;
+        return result ;
+    end;
+
+    function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_ULOGIC_VECTOR (length-1 downto 0);
+        -- pragma label_applies_to minus
+    begin
+        result := std_ulogic_vector( UNSIGNED(L) - UNSIGNED(R) ); -- pragma label minus
+        return  result ;
+    end;
+
+    function "-"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to minus
+    begin
+        result  := std_ulogic_vector( UNSIGNED(L) - R ); -- pragma label minus
+        return  result ;
+    end;
+
+    function "-"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to minus
+    begin
+        result  := std_ulogic_vector( L - UNSIGNED(R) ); -- pragma label minus
+        return   result ;
+    end;
+
+    function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to minus
+    begin
+        if R = '1' then
+           result  := std_ulogic_vector( UNSIGNED(L) - 1 );
+        else
+           result  := L;
+        end if;
+        return  result ;
+    end;
+
+    function "-"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to minus
+    begin
+        if L = '1' then
+           result  := std_ulogic_vector( 1 - UNSIGNED(R) );
+        else
+           result  := std_ulogic_vector( 0 - UNSIGNED(R) );
+        end if;
+        return  result ;
+    end;
+
+    function "*"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_ULOGIC_VECTOR ((L'length+R'length-1) downto 0);
+        -- pragma label_applies_to mult
+    begin
+        result := std_ulogic_vector( UNSIGNED(L) * UNSIGNED(R) ); -- pragma label mult
+        return result ;
+    end;
+
+  function "=" ( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l = unsigned(r);
+  end "=";
+  
+  function "/="( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l /= unsigned(r);
+  end "/=";
+  
+  function "<" ( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l < unsigned(r);
+  end "<";
+  
+  function "<="( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l <= unsigned(r);
+  end "<=";
+  
+  function ">" ( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l > unsigned(r);
+  end ">";
+  
+  function ">="( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l >= unsigned(r);
+  end ">=";
+  
+  function "=" ( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) = r;
+  end "=";
+  
+  function "/="( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) /= r;
+  end "/=";
+  
+  function "<" ( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) < r;
+  end "<";
+  
+  function "<="( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) <= r;
+  end "<=";
+  
+  function ">" ( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) > r;
+  end ">";
+  
+  function ">="( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) >= r;
+  end ">=";
+  
+  function "=" ( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l = unsigned(r) );
+  end "=";
+  
+  function "/="( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l /= unsigned(r) );
+  end "/=";
+  
+  function "<" ( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l < unsigned(r) );
+  end "<";
+  
+  function "<="( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l <= unsigned(r) );
+  end "<=";
+  
+  function ">" ( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l > unsigned(r) );
+  end ">";
+  
+  function ">="( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l >= unsigned(r) );
+  end ">=";
+  
+  function "=" ( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) = r );
+  end "=";
+  
+  function "/="( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) /= r );
+  end "/=";
+  
+  function "<" ( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) < r );
+  end "<";
+  
+  function "<="( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) <= r );
+  end "<=";
+  
+  function ">" ( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) > r );
+  end ">";
+  
+  function ">="( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) >= r );
+  end ">=";
+  
+  function to_integer( d : std_ulogic_vector ) return natural is
+  begin
+    return tconv( d );
+  end to_integer;
+  
+  function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector is
+  begin
+    return tconv( d, w );
+  end to_std_ulogic_vector;
+  
+end std_ulogic_unsigned;

rel/build/ip_user/a2x_axi/a2x_axi/src/support/power_logic_pkg.vhdl

@@ -0,0 +1,38 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package power_logic_pkg is
+
+  subtype power_logic is std_logic;
+  subtype power_logic_vector is std_logic_vector;
+  
+end package power_logic_pkg;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s18_s18.vhdl

@@ -0,0 +1,360 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm; 
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library UNIMACRO;
+use UNIMACRO.vcomponents.all;
+
+entity RAMB16_S18_S18 is
+	generic (
+		INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_A : bit_vector := X"000000000";
+		INIT_B : bit_vector := X"000000000";
+		SIM_COLLISION_CHECK : string := "ALL";   
+		SRVAL_A : bit_vector := X"000000000";
+		SRVAL_B : bit_vector := X"000000000";
+		WRITE_MODE_A : string := "WRITE_FIRST";  
+		WRITE_MODE_B : string := "WRITE_FIRST"   
+	);
+	port (
+		DOA : out std_logic_vector(15 downto 0);
+		DOB : out std_logic_vector(15 downto 0);
+		DOPA : out std_logic_vector(1 downto 0);
+		DOPB : out std_logic_vector(1 downto 0);
+		ADDRA : in std_logic_vector(9 downto 0);
+		ADDRB : in std_logic_vector(9 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(15 downto 0);
+		DIB : in std_logic_vector(15 downto 0);
+		DIPA : in std_logic_vector(1 downto 0);
+		DIPB : in std_logic_vector(1 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+end RAMB16_S18_S18;
+
+architecture RAMB16_S18_S18 of RAMB16_S18_S18 is
+
+signal DINA, DINB     : std_logic_vector(17 downto 0);
+signal DOUTA, DOUTB   : std_logic_vector(17 downto 0);
+signal SSRA_t, SSRB_t : std_logic;
+signal WEA_t, WEB_t   : std_logic_vector(1 downto 0);
+
+begin
+
+DINA   <= DIPA & DIA;
+DOPA   <= DOUTA(17 downto 16);
+DOA    <= DOUTA(15 downto 0);
+
+DINB   <= DIPB & DIB;
+DOPB   <= DOUTB(17 downto 16);
+DOB    <= DOUTB(15 downto 0);
+
+SSRA_t <= SSRA;
+SSRB_t <= SSRB;
+WEA_t  <= WEA & WEA;
+WEB_t  <= WEB & WEB;
+
+
+
+
+   
+   BRAM_0 : BRAM_TDP_MACRO
+   generic map (
+      BRAM_SIZE => "18Kb", 
+      DEVICE => "7SERIES", 
+      DOA_REG => 0, 
+      DOB_REG => 0, 
+      INIT_A => INIT_A, 
+      INIT_B => INIT_B, 
+      INIT_FILE => "NONE",
+      READ_WIDTH_A => 18,   
+      READ_WIDTH_B => 18,   
+      SIM_COLLISION_CHECK => "NONE",
+      SRVAL_A => SRVAL_A,   
+      SRVAL_B => SRVAL_A,   
+      WRITE_MODE_A => WRITE_MODE_A, 
+      WRITE_MODE_B => WRITE_MODE_B, 
+      WRITE_WIDTH_A => 18, 
+      WRITE_WIDTH_B => 18, 
+      INIT_00 => INIT_00,
+      INIT_01 => INIT_01,
+      INIT_02 => INIT_02,
+      INIT_03 => INIT_03,
+      INIT_04 => INIT_04,
+      INIT_05 => INIT_05,
+      INIT_06 => INIT_06,
+      INIT_07 => INIT_07,
+      INIT_08 => INIT_08,
+      INIT_09 => INIT_09,
+      INIT_0A => INIT_0A,
+      INIT_0B => INIT_0B,
+      INIT_0C => INIT_0C,
+      INIT_0D => INIT_0D,
+      INIT_0E => INIT_0E,
+      INIT_0F => INIT_0F,
+      INIT_10 => INIT_10,
+      INIT_11 => INIT_11,
+      INIT_12 => INIT_12,
+      INIT_13 => INIT_13,
+      INIT_14 => INIT_14,
+      INIT_15 => INIT_15,
+      INIT_16 => INIT_16,
+      INIT_17 => INIT_17,
+      INIT_18 => INIT_18,
+      INIT_19 => INIT_19,
+      INIT_1A => INIT_1A,
+      INIT_1B => INIT_1B,
+      INIT_1C => INIT_1C,
+      INIT_1D => INIT_1D,
+      INIT_1E => INIT_1E,
+      INIT_1F => INIT_1F,
+      INIT_20 => INIT_20,
+      INIT_21 => INIT_21,
+      INIT_22 => INIT_22,
+      INIT_23 => INIT_23,
+      INIT_24 => INIT_24,
+      INIT_25 => INIT_25,
+      INIT_26 => INIT_26,
+      INIT_27 => INIT_27,
+      INIT_28 => INIT_28,
+      INIT_29 => INIT_29,
+      INIT_2A => INIT_2A,
+      INIT_2B => INIT_2B,
+      INIT_2C => INIT_2C,
+      INIT_2D => INIT_2D,
+      INIT_2E => INIT_2E,
+      INIT_2F => INIT_2F,
+      INIT_30 => INIT_30,
+      INIT_31 => INIT_31,
+      INIT_32 => INIT_32,
+      INIT_33 => INIT_33,
+      INIT_34 => INIT_34,
+      INIT_35 => INIT_35,
+      INIT_36 => INIT_36,
+      INIT_37 => INIT_37,
+      INIT_38 => INIT_38,
+      INIT_39 => INIT_39,
+      INIT_3A => INIT_3A,
+      INIT_3B => INIT_3B,
+      INIT_3C => INIT_3C,
+      INIT_3D => INIT_3D,
+      INIT_3E => INIT_3E,
+      INIT_3F => INIT_3F,
+      
+      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      
+      INITP_00 => INITP_00,
+      INITP_01 => INITP_01,
+      INITP_02 => INITP_02,
+      INITP_03 => INITP_03,
+      INITP_04 => INITP_04,
+      INITP_05 => INITP_05,
+      INITP_06 => INITP_06,
+      INITP_07 => INITP_07,
+      
+      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
+   )
+   port map (
+      DOA => DOUTA,     
+      DOB => DOUTB,     
+      ADDRA => ADDRA,   
+      ADDRB => ADDRB,   
+      CLKA => CLKA,     
+      CLKB => CLKB,     
+      DIA => DINA,      
+      DIB => DINB,      
+      ENA => ENA,       
+      ENB => ENB,       
+      REGCEA => '1',    
+      REGCEB => '1',    
+      RSTA => SSRA_t,   
+      RSTB => SSRB_t,   
+      WEA => WEA_t,     
+      WEB => WEB_t      
+   );
+   
+
+
+end RAMB16_S18_S18;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s36_s36.vhdl

@@ -0,0 +1,364 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm; 
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library UNIMACRO;
+use UNIMACRO.vcomponents.all;
+
+entity RAMB16_S36_S36 is
+	generic (
+		INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_A : bit_vector := X"000000000";
+		INIT_B : bit_vector := X"000000000";
+		SIM_COLLISION_CHECK : string := "ALL";   
+		SRVAL_A : bit_vector := X"000000000";
+		SRVAL_B : bit_vector := X"000000000";
+		WRITE_MODE_A : string := "WRITE_FIRST";  
+		WRITE_MODE_B : string := "WRITE_FIRST"   
+	);
+	port (
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+end RAMB16_S36_S36;
+
+architecture RAMB16_S36_S36 of RAMB16_S36_S36 is
+
+signal ADDRA_10, ADDRB_10 : std_logic_vector(9 downto 0);
+signal DINA, DINB     : std_logic_vector(35 downto 0);
+signal DOUTA, DOUTB   : std_logic_vector(35 downto 0);
+signal SSRA_t, SSRB_t : std_logic;
+signal WEA_t, WEB_t   : std_logic_vector(3 downto 0);
+
+begin
+
+ADDRA_10 <= '0' & ADDRA;
+ADDRB_10 <= '0' & ADDRB;
+
+DINA   <= DIPA & DIA;
+DOPA   <= DOUTA(35 downto 32);
+DOA    <= DOUTA(31 downto 0);
+
+DINB   <= DIPB & DIB;
+DOPB   <= DOUTB(35 downto 32);
+DOB    <= DOUTB(31 downto 0);
+
+SSRA_t <= SSRA;
+SSRB_t <= SSRB;
+WEA_t  <= WEA & WEA & WEA & WEA;
+WEB_t  <= WEB & WEB & WEB & WEB;
+
+
+
+
+   
+   BRAM_0 : BRAM_TDP_MACRO
+   generic map (
+      BRAM_SIZE => "36Kb", 
+      DEVICE => "7SERIES", 
+      DOA_REG => 0, 
+      DOB_REG => 0, 
+      INIT_A => INIT_A, 
+      INIT_B => INIT_B, 
+      INIT_FILE => "NONE",
+      READ_WIDTH_A => 36,   
+      READ_WIDTH_B => 36,   
+      SIM_COLLISION_CHECK => "NONE",
+      SRVAL_A => SRVAL_A,   
+      SRVAL_B => SRVAL_A,   
+      WRITE_MODE_A => WRITE_MODE_A, 
+      WRITE_MODE_B => WRITE_MODE_B, 
+      WRITE_WIDTH_A => 36, 
+      WRITE_WIDTH_B => 36, 
+      INIT_00 => INIT_00,
+      INIT_01 => INIT_01,
+      INIT_02 => INIT_02,
+      INIT_03 => INIT_03,
+      INIT_04 => INIT_04,
+      INIT_05 => INIT_05,
+      INIT_06 => INIT_06,
+      INIT_07 => INIT_07,
+      INIT_08 => INIT_08,
+      INIT_09 => INIT_09,
+      INIT_0A => INIT_0A,
+      INIT_0B => INIT_0B,
+      INIT_0C => INIT_0C,
+      INIT_0D => INIT_0D,
+      INIT_0E => INIT_0E,
+      INIT_0F => INIT_0F,
+      INIT_10 => INIT_10,
+      INIT_11 => INIT_11,
+      INIT_12 => INIT_12,
+      INIT_13 => INIT_13,
+      INIT_14 => INIT_14,
+      INIT_15 => INIT_15,
+      INIT_16 => INIT_16,
+      INIT_17 => INIT_17,
+      INIT_18 => INIT_18,
+      INIT_19 => INIT_19,
+      INIT_1A => INIT_1A,
+      INIT_1B => INIT_1B,
+      INIT_1C => INIT_1C,
+      INIT_1D => INIT_1D,
+      INIT_1E => INIT_1E,
+      INIT_1F => INIT_1F,
+      INIT_20 => INIT_20,
+      INIT_21 => INIT_21,
+      INIT_22 => INIT_22,
+      INIT_23 => INIT_23,
+      INIT_24 => INIT_24,
+      INIT_25 => INIT_25,
+      INIT_26 => INIT_26,
+      INIT_27 => INIT_27,
+      INIT_28 => INIT_28,
+      INIT_29 => INIT_29,
+      INIT_2A => INIT_2A,
+      INIT_2B => INIT_2B,
+      INIT_2C => INIT_2C,
+      INIT_2D => INIT_2D,
+      INIT_2E => INIT_2E,
+      INIT_2F => INIT_2F,
+      INIT_30 => INIT_30,
+      INIT_31 => INIT_31,
+      INIT_32 => INIT_32,
+      INIT_33 => INIT_33,
+      INIT_34 => INIT_34,
+      INIT_35 => INIT_35,
+      INIT_36 => INIT_36,
+      INIT_37 => INIT_37,
+      INIT_38 => INIT_38,
+      INIT_39 => INIT_39,
+      INIT_3A => INIT_3A,
+      INIT_3B => INIT_3B,
+      INIT_3C => INIT_3C,
+      INIT_3D => INIT_3D,
+      INIT_3E => INIT_3E,
+      INIT_3F => INIT_3F,
+      
+      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      
+      INITP_00 => INITP_00,
+      INITP_01 => INITP_01,
+      INITP_02 => INITP_02,
+      INITP_03 => INITP_03,
+      INITP_04 => INITP_04,
+      INITP_05 => INITP_05,
+      INITP_06 => INITP_06,
+      INITP_07 => INITP_07,
+      
+      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
+   )
+   port map (
+      DOA => DOUTA,     
+      DOB => DOUTB,     
+      ADDRA => ADDRA_10,  
+      ADDRB => ADDRB_10,  
+      CLKA => CLKA,     
+      CLKB => CLKB,     
+      DIA => DINA,      
+      DIB => DINB,      
+      ENA => ENA,       
+      ENB => ENB,       
+      REGCEA => '1',    
+      REGCEB => '1',    
+      RSTA => SSRA_t,   
+      RSTB => SSRB_t,   
+      WEA => WEA_t,     
+      WEB => WEB_t      
+   );
+   
+
+
+end RAMB16_S36_S36;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s9_s9.vhdl

@@ -0,0 +1,360 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm; 
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library UNIMACRO;
+use UNIMACRO.vcomponents.all;
+
+entity RAMB16_S9_S9 is
+	generic (
+		INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_A : bit_vector := X"000000000";
+		INIT_B : bit_vector := X"000000000";
+		SIM_COLLISION_CHECK : string := "ALL";   
+		SRVAL_A : bit_vector := X"000000000";
+		SRVAL_B : bit_vector := X"000000000";
+		WRITE_MODE_A : string := "WRITE_FIRST";  
+		WRITE_MODE_B : string := "WRITE_FIRST"   
+	);
+	port (
+		DOA : out std_logic_vector(7 downto 0);
+		DOB : out std_logic_vector(7 downto 0);
+		DOPA : out std_logic_vector(0 downto 0);
+		DOPB : out std_logic_vector(0 downto 0);
+		ADDRA : in std_logic_vector(10 downto 0);
+		ADDRB : in std_logic_vector(10 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(7 downto 0);
+		DIB : in std_logic_vector(7 downto 0);
+		DIPA : in std_logic_vector(0 downto 0);
+		DIPB : in std_logic_vector(0 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+end RAMB16_S9_S9;
+
+architecture RAMB16_S9_S9 of RAMB16_S9_S9 is
+
+signal DINA, DINB     : std_logic_vector(8 downto 0);
+signal DOUTA, DOUTB   : std_logic_vector(8 downto 0);
+signal SSRA_t, SSRB_t : std_logic;
+signal WEA_t, WEB_t   : std_logic_vector(0 downto 0);
+
+begin
+
+DINA   <= DIPA & DIA;
+DOPA(0) <= DOUTA(8);
+DOA    <= DOUTA(7 downto 0);
+
+DINB   <= DIPB & DIB;
+DOPB(0) <= DOUTB(8);
+DOB    <= DOUTB(7 downto 0);
+
+SSRA_t <= SSRA;
+SSRB_t <= SSRB;
+WEA_t(0)  <= WEA;
+WEB_t(0)  <= WEB;
+
+
+
+
+   
+   BRAM_0 : BRAM_TDP_MACRO
+   generic map (
+      BRAM_SIZE => "18Kb", 
+      DEVICE => "7SERIES", 
+      DOA_REG => 0, 
+      DOB_REG => 0, 
+      INIT_A => INIT_A, 
+      INIT_B => INIT_B, 
+      INIT_FILE => "NONE",
+      READ_WIDTH_A => 9,   
+      READ_WIDTH_B => 9,   
+      SIM_COLLISION_CHECK => "NONE",
+      SRVAL_A => SRVAL_A,   
+      SRVAL_B => SRVAL_A,   
+      WRITE_MODE_A => WRITE_MODE_A, 
+      WRITE_MODE_B => WRITE_MODE_B, 
+      WRITE_WIDTH_A => 9, 
+      WRITE_WIDTH_B => 9, 
+      INIT_00 => INIT_00,
+      INIT_01 => INIT_01,
+      INIT_02 => INIT_02,
+      INIT_03 => INIT_03,
+      INIT_04 => INIT_04,
+      INIT_05 => INIT_05,
+      INIT_06 => INIT_06,
+      INIT_07 => INIT_07,
+      INIT_08 => INIT_08,
+      INIT_09 => INIT_09,
+      INIT_0A => INIT_0A,
+      INIT_0B => INIT_0B,
+      INIT_0C => INIT_0C,
+      INIT_0D => INIT_0D,
+      INIT_0E => INIT_0E,
+      INIT_0F => INIT_0F,
+      INIT_10 => INIT_10,
+      INIT_11 => INIT_11,
+      INIT_12 => INIT_12,
+      INIT_13 => INIT_13,
+      INIT_14 => INIT_14,
+      INIT_15 => INIT_15,
+      INIT_16 => INIT_16,
+      INIT_17 => INIT_17,
+      INIT_18 => INIT_18,
+      INIT_19 => INIT_19,
+      INIT_1A => INIT_1A,
+      INIT_1B => INIT_1B,
+      INIT_1C => INIT_1C,
+      INIT_1D => INIT_1D,
+      INIT_1E => INIT_1E,
+      INIT_1F => INIT_1F,
+      INIT_20 => INIT_20,
+      INIT_21 => INIT_21,
+      INIT_22 => INIT_22,
+      INIT_23 => INIT_23,
+      INIT_24 => INIT_24,
+      INIT_25 => INIT_25,
+      INIT_26 => INIT_26,
+      INIT_27 => INIT_27,
+      INIT_28 => INIT_28,
+      INIT_29 => INIT_29,
+      INIT_2A => INIT_2A,
+      INIT_2B => INIT_2B,
+      INIT_2C => INIT_2C,
+      INIT_2D => INIT_2D,
+      INIT_2E => INIT_2E,
+      INIT_2F => INIT_2F,
+      INIT_30 => INIT_30,
+      INIT_31 => INIT_31,
+      INIT_32 => INIT_32,
+      INIT_33 => INIT_33,
+      INIT_34 => INIT_34,
+      INIT_35 => INIT_35,
+      INIT_36 => INIT_36,
+      INIT_37 => INIT_37,
+      INIT_38 => INIT_38,
+      INIT_39 => INIT_39,
+      INIT_3A => INIT_3A,
+      INIT_3B => INIT_3B,
+      INIT_3C => INIT_3C,
+      INIT_3D => INIT_3D,
+      INIT_3E => INIT_3E,
+      INIT_3F => INIT_3F,
+      
+      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      
+      INITP_00 => INITP_00,
+      INITP_01 => INITP_01,
+      INITP_02 => INITP_02,
+      INITP_03 => INITP_03,
+      INITP_04 => INITP_04,
+      INITP_05 => INITP_05,
+      INITP_06 => INITP_06,
+      INITP_07 => INITP_07,
+      
+      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
+   )
+   port map (
+      DOA => DOUTA,     
+      DOB => DOUTB,     
+      ADDRA => ADDRA,   
+      ADDRB => ADDRB,   
+      CLKA => CLKA,     
+      CLKB => CLKB,     
+      DIA => DINA,      
+      DIB => DINB,      
+      ENA => ENA,       
+      ENB => ENB,       
+      REGCEA => '1',    
+      REGCEB => '1',    
+      RSTA => SSRA_t,   
+      RSTB => SSRB_t,   
+      WEA => WEA_t,     
+      WEB => WEB_t      
+   );
+   
+
+
+end RAMB16_S9_S9;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x168_1w_0.vhdl

@@ -0,0 +1,338 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; 
+             use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; 
+use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_128x168_1w_0 is
+  generic (addressable_ports : positive := 128; 
+           addressbus_width : positive := 7;    
+           port_bitwidth : positive := 168;     
+           ways : positive := 1;                
+           expand_type : integer := 1);         
+  port (
+    gnd                : inout power_logic;
+    vdd                : inout power_logic;
+    vcs                : inout power_logic;
+    
+    nclk              : in clk_logic;
+    act               : in std_ulogic;
+    ccflush_dc        : in std_ulogic;
+    scan_dis_dc_b     : in std_ulogic;
+    scan_diag_dc      : in std_ulogic;
+
+    abst_scan_in    : in std_ulogic;
+    repr_scan_in    : in std_ulogic;
+    time_scan_in    : in std_ulogic;
+    abst_scan_out   : out std_ulogic;
+    repr_scan_out   : out std_ulogic;
+    time_scan_out   : out std_ulogic;
+    
+    lcb_d_mode_dc              : in std_ulogic;
+    lcb_clkoff_dc_b            : in std_ulogic;
+    lcb_act_dis_dc             : in std_ulogic;
+    lcb_mpw1_dc_b              : in std_ulogic_vector(0 to 4);
+    lcb_mpw2_dc_b              : in std_ulogic;
+    lcb_delay_lclkr_dc         : in std_ulogic_vector(0 to 4);
+
+    lcb_sg_1              : in std_ulogic;
+    lcb_time_sg_0         : in std_ulogic;
+    lcb_repr_sg_0         : in std_ulogic;
+    
+    lcb_abst_sl_thold_0   : in std_ulogic;
+    lcb_repr_sl_thold_0   : in std_ulogic;
+    lcb_time_sl_thold_0   : in std_ulogic;
+    lcb_ary_nsl_thold_0   : in std_ulogic;
+    lcb_bolt_sl_thold_0   : in std_ulogic; 
+
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_en_1                  : in std_ulogic;
+    din_abist                   : in std_ulogic_vector(0 to 3);
+    abist_cmp_en                : in std_ulogic;
+    abist_raw_b_dc              : in std_ulogic;
+    data_cmp_abist              : in std_ulogic_vector(0 to 3);
+    addr_abist                  : in std_ulogic_vector(0 to 6);
+    r_wb_abist                  : in std_ulogic;
+
+    pc_bo_enable_2                 : in    std_ulogic; 
+    pc_bo_reset                    : in    std_ulogic; 
+    pc_bo_unload                   : in    std_ulogic;
+    pc_bo_repair                   : in    std_ulogic; 
+    pc_bo_shdata                   : in    std_ulogic; 
+    pc_bo_select                   : in    std_ulogic; 
+    bo_pc_failout                  : out   std_ulogic; 
+    bo_pc_diagloop                 : out   std_ulogic;
+    tri_lcb_mpw1_dc_b              : in    std_ulogic;
+    tri_lcb_mpw2_dc_b              : in    std_ulogic;
+    tri_lcb_delay_lclkr_dc         : in    std_ulogic;
+    tri_lcb_clkoff_dc_b            : in    std_ulogic;
+    tri_lcb_act_dis_dc             : in    std_ulogic;
+
+    write_enable      : in std_ulogic;
+    addr              : in std_ulogic_vector (0 to addressbus_width-1);
+    data_in           : in std_ulogic_vector (0 to port_bitwidth-1);
+    data_out          : out std_ulogic_vector(0 to port_bitwidth-1)
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_128x168_1w_0;
+
+architecture tri_128x168_1w_0 of tri_128x168_1w_0 is
+
+constant wga_base_width : integer := 168;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+constant way : std_ulogic_vector(0 to 0) := "0";
+
+
+type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal write_enable_d     : std_ulogic;
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      addr_latch: tri_rlmreg_p
+        generic map (width => addr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr,
+                  dout        => addr_l2 );
+
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= act and write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+  abst_scan_out <= abst_scan_in;
+  repr_scan_out <= repr_scan_in;
+  time_scan_out <= time_scan_in;
+
+  bo_pc_failout  <= '0';
+  bo_pc_diagloop <= '0';
+
+  end generate um;
+  -- synopsys translate_on
+
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+      -- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+      -- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal ramb_data_in       : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+      signal ramb_data_out      : RAMB_DATA_ARRAY(way'range);
+      signal ramb_addr          : std_logic_vector(0 to ramb_base_addr - 1);
+
+      signal write              : std_ulogic_vector(way'range);
+      signal tidn               : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      add0: if (addressbus_width < ramb_base_addr) generate
+      begin
+        ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr );
+      end generate;
+      add1: if (addressbus_width >= ramb_base_addr) generate
+      begin
+        ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+      end generate;
+
+      din: for i in ramb_data_in'range generate
+      begin
+        R0: if(i <  port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate;
+        R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate;
+      end generate;
+
+      aw: for w in way'range generate begin
+        write(w) <= write_enable;
+
+        ax: for x in 0 to (ramb_width_mult - 1) generate begin
+          ram: RAMB16_S36_S36
+            -- pragma translate_off
+            generic map(
+                        sim_collision_check => "none")
+            -- pragma translate_on
+            port map(
+		DOA   => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DOB   => open,
+		DOPA  => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DOPB  => open,
+		ADDRA => ramb_addr,
+		ADDRB => ramb_addr,
+		CLKA  => nclk.clk,
+		CLKB  => tidn,
+		DIA   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIB   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIPA  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DIPB  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		ENA   => act,
+		ENB   => tidn,
+		SSRA  => nclk.sreset,
+		SSRB  => tidn,
+		WEA   => write(w),
+		WEB   => tidn
+	  );
+
+        end generate ax;
+
+        data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) );
+
+      end generate aw;
+      
+  abst_scan_out <= abst_scan_in;
+  repr_scan_out <= repr_scan_in;
+  time_scan_out <= time_scan_in;
+
+  bo_pc_failout  <= '0';
+  bo_pc_diagloop <= '0';
+
+  unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & ccflush_dc & scan_dis_dc_b & scan_diag_dc & lcb_d_mode_dc
+                       & lcb_clkoff_dc_b & lcb_act_dis_dc & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                       & lcb_delay_lclkr_dc & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0
+                       & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 & lcb_time_sl_thold_0
+                       & lcb_ary_nsl_thold_0 & lcb_bolt_sl_thold_0 & tc_lbist_ary_wrt_thru_dc
+                       & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist
+                       & addr_abist & r_wb_abist & pc_bo_enable_2 & pc_bo_reset
+                       & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+  end generate a;
+
+end tri_128x168_1w_0;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x16_1r1w_1.vhdl

@@ -0,0 +1,466 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;  use ieee.std_logic_1164.all;
+library support; 
+                 use support.power_logic_pkg.all;
+library ibm; 
+             use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_128x16_1r1w_1 is
+  generic (addressable_ports : positive := 128; 
+           addressbus_width : positive := 7;    
+           port_bitwidth : positive := 16;      
+           ways : positive := 1;                
+           expand_type : integer := 1);         
+port (
+    vdd                          : INOUT power_logic; 
+    vcs                          : INOUT power_logic; 
+    gnd                          : INOUT power_logic; 
+  
+    nclk                         : IN clk_logic;
+
+    rd_act                             : IN std_ulogic;
+    wr_act            		       : IN std_ulogic;
+
+    lcb_d_mode_dc                : IN std_ulogic;
+    lcb_clkoff_dc_b              : IN std_ulogic;
+    lcb_mpw1_dc_b                : IN std_ulogic_vector(0 TO 4);
+    lcb_mpw2_dc_b                : IN std_ulogic;		
+    lcb_delay_lclkr_dc           : IN std_ulogic_vector(0 TO 4);		
+
+    ccflush_dc                   : IN  std_ulogic;
+    scan_dis_dc_b                : IN  std_ulogic;		
+    scan_diag_dc                 : IN  std_ulogic;
+    func_scan_in         : IN std_ulogic;
+    func_scan_out        : OUT std_ulogic;
+
+    lcb_sg_0              : IN std_ulogic;
+    lcb_sl_thold_0_b      : IN std_ulogic;
+    lcb_time_sl_thold_0        : IN std_ulogic;
+    lcb_abst_sl_thold_0        : IN std_ulogic;
+    lcb_ary_nsl_thold_0        : IN std_ulogic;
+    lcb_repr_sl_thold_0        : IN std_ulogic;
+    time_scan_in         : IN std_ulogic;
+    time_scan_out        : OUT std_ulogic;
+    abst_scan_in         : IN std_ulogic;
+    abst_scan_out        : OUT std_ulogic;
+    repr_scan_in         : IN std_ulogic;
+    repr_scan_out        : OUT std_ulogic;
+
+    abist_di                     : IN std_ulogic_vector(0 TO 3);
+    abist_bw_odd                 : IN std_ulogic;
+    abist_bw_even                : IN std_ulogic;
+    abist_wr_adr                 : IN std_ulogic_vector(0 TO 6);
+    wr_abst_act                  : IN std_ulogic;
+    abist_rd0_adr                : IN std_ulogic_vector(0 TO 6);
+    rd0_abst_act                 : IN std_ulogic;
+    tc_lbist_ary_wrt_thru_dc     : IN std_ulogic;
+    abist_ena_1                  : IN std_ulogic;
+    abist_g8t_rd0_comp_ena       : IN std_ulogic;
+    abist_raw_dc_b               : IN std_ulogic;
+    obs0_abist_cmp               : IN std_ulogic_vector(0 TO 3);
+
+    lcb_bolt_sl_thold_0         : in    std_ulogic;
+    pc_bo_enable_2              : in    std_ulogic; 
+    pc_bo_reset                 : in    std_ulogic; 
+    pc_bo_unload                : in    std_ulogic; 
+    pc_bo_repair                : in    std_ulogic; 
+    pc_bo_shdata                : in    std_ulogic; 
+    pc_bo_select                : in    std_ulogic; 
+    bo_pc_failout               : out   std_ulogic; 
+    bo_pc_diagloop              : out   std_ulogic;
+    tri_lcb_mpw1_dc_b           : in    std_ulogic;
+    tri_lcb_mpw2_dc_b           : in    std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in    std_ulogic;
+    tri_lcb_clkoff_dc_b         : in    std_ulogic;
+    tri_lcb_act_dis_dc          : in    std_ulogic;
+
+    bw                           : IN std_ulogic_vector( 0 TO 15 );  
+    wr_adr                       : IN std_ulogic_vector( 0 TO 6 );
+    rd_adr                       : IN std_ulogic_vector( 0 TO 6 );  
+    di                		 : IN std_ulogic_vector( 0 TO 15 );
+    do                        : OUT std_ulogic_vector( 0 TO 15 )
+		
+   );
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity tri_128x16_1r1w_1;
+
+architecture tri_128x16_1r1w_1 of tri_128x16_1r1w_1 is
+
+begin
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+
+     constant rd_addr_offset       :  natural := 0;
+     constant wr_addr_offset       :  natural := rd_addr_offset + addressbus_width;
+     constant write_enable_offset  :  natural := wr_addr_offset + addressbus_width;
+     constant data_in_offset       :  natural := write_enable_offset + port_bitwidth;
+     constant data_out_offset      :  natural := data_in_offset + port_bitwidth;
+     constant array_offset         :  natural := data_out_offset + port_bitwidth;
+     constant scan_right           :  natural := array_offset + addressable_ports*port_bitwidth*ways - 1;
+
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal rd_addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal wr_addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal write_enable_d     : std_ulogic_vector(0 to port_bitwidth-1);
+      signal write_enable_l2    : std_ulogic_vector(0 to port_bitwidth-1);
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal data_out_d          : std_ulogic_vector(0 to port_bitwidth-1);
+      signal data_out_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal siv                      : std_ulogic_vector(0 to scan_right);
+      signal sov                      : std_ulogic_vector(0 to scan_right);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      rd_addr_latch: tri_rlmreg_p
+        generic map (width => rd_adr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => rd_act,
+                  scin        => siv(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1),
+                  scout       => sov(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1),
+                  din         => rd_adr,
+                  dout        => rd_addr_l2 );
+
+      wr_addr_latch: tri_rlmreg_p
+        generic map (width => wr_adr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1),
+                  scout       => sov(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1),
+                  din         => wr_adr,
+                  dout        => wr_addr_l2 );
+
+
+
+      write_enable_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(write_enable_offset to write_enable_offset+write_enable_l2'length-1),
+                  scout       => sov(write_enable_offset to write_enable_offset+write_enable_l2'length-1),
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(data_in_offset to data_in_offset+data_in_l2'length-1),
+                  scout       => sov(data_in_offset to data_in_offset+data_in_l2'length-1),
+                  din         => di,
+                  dout        => data_in_l2 );
+
+      data_out_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(data_out_offset to data_out_offset+data_out_l2'length-1),
+                  scout       => sov(data_out_offset to data_out_offset+data_out_l2'length-1),
+                  din         => data_out_d,
+                  dout        => data_out_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => siv(array_offset to array_offset+array_l2'length-1),
+                  scout       => sov(array_offset to array_offset+array_l2'length-1),
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= bw when wr_act='1' else (others => '0');
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when ( write_enable_l2(x)='1' and wr_addr_l2 = tconv(y, addressbus_width)) 
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out_d(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth);
+      data_out_d(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1);
+      data_out_d(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2);
+      data_out_d(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3);
+      data_out_d(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4);
+      data_out_d(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5);
+      data_out_d(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6);
+      data_out_d(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7);
+      data_out_d(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8);
+      data_out_d(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9);
+      data_out_d(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10);
+      data_out_d(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11);
+      data_out_d(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12);
+      data_out_d(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13);
+      data_out_d(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14);
+      data_out_d(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15);
+
+      do(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth);
+      do(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1);
+      do(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2);
+      do(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3);
+      do(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4);
+      do(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5);
+      do(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6);
+      do(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7);
+      do(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8);
+      do(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9);
+      do(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10);
+      do(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11);
+      do(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12);
+      do(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13);
+      do(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14);
+      do(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15);
+
+  siv(0 to scan_right) <= sov(1 to scan_right) & func_scan_in;
+  func_scan_out <= sov(0);
+  
+  time_scan_out <= time_scan_in;
+  abst_scan_out <= abst_scan_in;
+  repr_scan_out <= repr_scan_in;
+
+  bo_pc_failout  <= '0';
+  bo_pc_diagloop <= '0';
+
+  end generate um;
+  -- synopsys translate_on
+
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+
+
+-- pragma translate_off
+-- pragma translate_on
+
+
+
+signal clk,clk2x                          : std_ulogic;
+signal b0addra,         b0addrb           : std_ulogic_vector(0 to 8);
+signal wea,             web               : std_ulogic;
+signal wren_a              : std_ulogic;
+signal reset_q                            : std_ulogic;
+signal gate_fq,         gate_d            : std_ulogic;
+signal r_data_out_1_d,  r_data_out_1_fq   : std_ulogic_vector(0 to 35);
+signal w_data_in_0                        : std_ulogic_vector(0 to 35);
+
+signal r_data_out_0_bram                  : std_logic_vector(0 to 35);
+signal r_data_out_1_bram                  : std_logic_vector(0 to 35);
+
+signal toggle_d     : std_ulogic;
+signal toggle_q     : std_ulogic;
+signal toggle2x_d   : std_ulogic;
+signal toggle2x_q   : std_ulogic;
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+clk   <= nclk.clk;
+clk2x <= nclk.clk2x;
+
+rlatch: process (clk) begin
+    if(rising_edge(clk)) then
+      reset_q              <= nclk.sreset;
+    end if;
+end process;
+
+
+tlatch: process (nclk.clk,reset_q)
+begin
+   if(rising_edge(nclk.clk)) then
+      if (reset_q = '1') then
+         toggle_q  <= '1';
+      else
+         toggle_q  <= toggle_d;
+      end if;
+    end if;
+end process;
+
+flatch: process (nclk.clk2x)
+begin
+   if(rising_edge(nclk.clk2x)) then
+      toggle2x_q <= toggle2x_d;
+      gate_fq  <= gate_d;
+      r_data_out_1_fq   <= r_data_out_1_d;
+   end if;
+end process;
+
+toggle_d   <= not toggle_q;
+toggle2x_d <= toggle_q;
+
+gate_d <= not(toggle_q xor toggle2x_q);
+
+
+
+
+
+b0addra(2 to 8)   <= wr_adr;
+b0addrb(2 to 8)   <= rd_adr;
+
+b0addra(0 to 1) <= "00";
+b0addrb(0 to 1) <= "00";
+
+
+
+wren_a <= '1' when bw /= "0000000000000000" else '0';
+wea         <= wren_a and not(gate_fq); 
+web         <= '0';
+w_data_in_0(0) <= di(0) when bw(0)='1' else r_data_out_0_bram(0);
+w_data_in_0(1) <= di(1) when bw(1)='1' else r_data_out_0_bram(1);
+w_data_in_0(2) <= di(2) when bw(2)='1' else r_data_out_0_bram(2);
+w_data_in_0(3) <= di(3) when bw(3)='1' else r_data_out_0_bram(3);
+w_data_in_0(4) <= di(4) when bw(4)='1' else r_data_out_0_bram(4);
+w_data_in_0(5) <= di(5) when bw(5)='1' else r_data_out_0_bram(5);
+w_data_in_0(6) <= di(6) when bw(6)='1' else r_data_out_0_bram(6);
+w_data_in_0(7) <= di(7) when bw(7)='1' else r_data_out_0_bram(7);
+w_data_in_0(8) <= di(8) when bw(8)='1' else r_data_out_0_bram(8);
+w_data_in_0(9) <= di(9) when bw(9)='1' else r_data_out_0_bram(9);
+w_data_in_0(10) <= di(10) when bw(10)='1' else r_data_out_0_bram(10);
+w_data_in_0(11) <= di(11) when bw(11)='1' else r_data_out_0_bram(11);
+w_data_in_0(12) <= di(12) when bw(12)='1' else r_data_out_0_bram(12);
+w_data_in_0(13) <= di(13) when bw(13)='1' else r_data_out_0_bram(13);
+w_data_in_0(14) <= di(14) when bw(14)='1' else r_data_out_0_bram(14);
+w_data_in_0(15) <= di(15) when bw(15)='1' else r_data_out_0_bram(15);
+w_data_in_0(16 to 35) <= (others => '0');
+
+r_data_out_1_d <= std_ulogic_vector(r_data_out_1_bram);
+
+bram0a : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                       clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => reset_q,
+	               ssrb  => reset_q,
+	               addra => std_logic_vector(b0addra),
+	               addrb => std_logic_vector(b0addrb),
+	               dia   => std_logic_vector(w_data_in_0(0 to 31)),
+	               dib   => (others => '0'),
+                       doa   => r_data_out_0_bram(0 to 31),
+                       dob   => r_data_out_1_bram(0 to 31),
+                       dopa  => r_data_out_0_bram(32 to 35),
+                       dopb  => r_data_out_1_bram(32 to 35),
+	               dipa  => std_logic_vector(w_data_in_0(32 to 35)),
+	               dipb  => (others => '0'),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea,
+	               web   => web
+	               );
+
+
+do   <= r_data_out_1_fq(0 to 15);
+
+func_scan_out <= func_scan_in;
+time_scan_out <= time_scan_in;
+abst_scan_out <= abst_scan_in;
+repr_scan_out <= repr_scan_in;
+
+bo_pc_failout  <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( std_ulogic_vector(r_data_out_0_bram(16 to 35)) & rd_act & wr_act
+                       & lcb_d_mode_dc & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                       & lcb_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc
+                       & lcb_sg_0 & lcb_sl_thold_0_b & lcb_time_sl_thold_0 & lcb_abst_sl_thold_0
+                       & lcb_ary_nsl_thold_0 & lcb_repr_sl_thold_0 & abist_di & abist_bw_odd
+                       & abist_bw_even & abist_wr_adr & wr_abst_act & abist_rd0_adr & rd0_abst_act
+                       & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                       & abist_raw_dc_b & obs0_abist_cmp & lcb_bolt_sl_thold_0 & pc_bo_enable_2
+                       & pc_bo_reset & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate a;
+
+
+end architecture tri_128x16_1r1w_1;
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w.vhdl

@@ -0,0 +1,411 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use ibm.std_ulogic_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+
+entity tri_144x78_2r2w is
+generic(
+   expand_type                         :     integer :=  1);
+port (
+   vdd                            :inout power_logic;    
+   gnd                            :inout power_logic;    
+   nclk                           :in   clk_logic;                 
+   abist_en                       :in   std_ulogic;  
+   abist_raw_dc_b                 :in   std_ulogic;  
+   r0e_abist_comp_en              :in   std_ulogic;  
+   r1e_abist_comp_en              :in   std_ulogic;  
+   lbist_en                      :in   std_ulogic;  
+
+   lcb_act_dis_dc                 :in   std_ulogic; 
+   lcb_clkoff_dc_b                :in   std_ulogic_vector(0 to 1);
+   lcb_d_mode_dc                  :in   std_ulogic;
+   lcb_delay_lclkr_dc             :in   std_ulogic_vector(0 to 9); 
+   lcb_fce_0                      :in   std_ulogic; 
+   lcb_mpw1_dc_b                  :in   std_ulogic_vector(1 to 9); 
+   lcb_mpw2_dc_b                  :in   std_ulogic; 
+   lcb_scan_diag_dc               :in   std_ulogic; 
+   lcb_scan_dis_dc_b              :in   std_ulogic; 
+   lcb_sg_0                       :in   std_ulogic; 
+   lcb_time_sg_0                  :in   std_ulogic;
+   lcb_obs0_sg_0                  :in   std_ulogic; 
+   lcb_obs1_sg_0                  :in   std_ulogic; 
+   lcb_obs0_sl_thold_0            :in   std_ulogic; 
+   lcb_obs1_sl_thold_0            :in   std_ulogic; 
+
+   lcb_abst_sl_thold_0            :in   std_ulogic;  
+   lcb_time_sl_thold_0            :in   std_ulogic; 
+   lcb_ary_nsl_thold_0            :in   std_ulogic;  
+
+   r_scan_in                      :in   std_ulogic;                 
+   r_scan_out                     :out  std_ulogic;   
+   w_scan_in                      :in   std_ulogic;                 
+   w_scan_out                     :out  std_ulogic;   
+   time_scan_in                   :in   std_ulogic; 
+   time_scan_out                  :out  std_ulogic; 
+   obs0_scan_in                   :in   std_ulogic; 
+   obs0_scan_out                  :out  std_ulogic; 
+   obs1_scan_in                   :in   std_ulogic; 
+   obs1_scan_out                  :out  std_ulogic; 
+
+   lcb_bolt_sl_thold_0            :in   std_ulogic;
+   pc_bo_enable_2                 :in   std_ulogic; 
+   pc_bo_reset                    :in   std_ulogic; 
+   pc_bo_unload                   :in   std_ulogic;
+   pc_bo_load                     :in   std_ulogic;
+   pc_bo_shdata                   :in   std_ulogic; 
+   pc_bo_select                   :in   std_ulogic; 
+   bo_pc_failout                  :out  std_ulogic; 
+   bo_pc_diagloop                 :out  std_ulogic;
+   tri_lcb_mpw1_dc_b              :in    std_ulogic;
+   tri_lcb_mpw2_dc_b              :in    std_ulogic;
+   tri_lcb_delay_lclkr_dc         :in    std_ulogic;
+   tri_lcb_clkoff_dc_b            :in    std_ulogic;
+   tri_lcb_act_dis_dc             :in    std_ulogic;
+
+   r0e_act                        :in   std_ulogic;                 
+   r0e_en_func                    :in   std_ulogic;                 
+   r0e_en_abist                   :in   std_ulogic;                 
+   r0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r0e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r0e_data_out                   :out  std_ulogic_vector(0 to 77); 
+   r0e_byp_e                      :in   std_ulogic; 
+   r0e_byp_l                      :in   std_ulogic; 
+   r0e_byp_r                      :in   std_ulogic;
+   r0e_sel_lbist                  :in   std_ulogic; 
+
+   r1e_act                        :in   std_ulogic;                 
+   r1e_en_func                    :in   std_ulogic;                 
+   r1e_en_abist                   :in   std_ulogic;                 
+   r1e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r1e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r1e_data_out                   :out  std_ulogic_vector(0 to 77);
+   r1e_byp_e                      :in   std_ulogic; 
+   r1e_byp_l                      :in   std_ulogic; 
+   r1e_byp_r                      :in   std_ulogic;
+   r1e_sel_lbist                  :in   std_ulogic; 
+
+   w0e_act                        :in   std_ulogic;                 
+   w0e_en_func                    :in   std_ulogic;                 
+   w0e_en_abist                   :in   std_ulogic;                 
+   w0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0e_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0e_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0e_data_abist                 :in   std_ulogic_vector(0 to 3);
+
+   w0l_act                        :in   std_ulogic;                 
+   w0l_en_func                    :in   std_ulogic;                 
+   w0l_en_abist                   :in   std_ulogic;                 
+   w0l_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0l_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0l_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0l_data_abist                 :in   std_ulogic_vector(0 to 3) );
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity   tri_144x78_2r2w;
+architecture tri_144x78_2r2w of tri_144x78_2r2w is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal  tilo                           : std_ulogic;
+signal  tihi                           : std_ulogic;
+signal  zeross                         : std_logic_vector(0 to 3); 
+
+signal  correct_clk                    : std_ulogic;
+signal  clk2x                          : std_ulogic;
+signal  reset                          : std_ulogic;
+signal  reset_hi                       : std_ulogic;
+signal  reset_lo                       : std_ulogic;
+signal  reset_q                        : std_ulogic;
+signal  sinit0_q        : std_logic;
+signal  sinit1_q        : std_logic;
+signal  flipper_d                      : std_ulogic;
+signal  flipper_q                      : std_ulogic;
+
+signal  doutb0                         : std_logic_vector(0 to 77);
+signal  doutb0_q                       : std_ulogic_vector(0 to 77);
+signal dinfa0_par                      : std_logic_vector(64 to 95);
+signal doutb0_par                      : std_logic_vector(64 to 95);
+signal  weaf                           : std_logic;
+signal  addra                          : std_logic_vector(0 to 8); 
+signal  addrb0                         : std_logic_vector(0 to 8); 
+signal  dinfa                          : std_logic_vector(0 to 77); 
+signal  dinfb                          : std_logic_vector(0 to 31); 
+
+signal  w0e_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_en_q                       : std_ulogic;
+signal  w0l_addr_q                     : std_ulogic_vector(0 to 7);
+signal  r1e_addr_q                     : std_ulogic_vector(0 to 7);
+
+signal   r0e_byp_e_q                   :   std_ulogic; 
+signal   r0e_byp_l_q                   :   std_ulogic; 
+signal   r1e_byp_e_q                   :   std_ulogic; 
+signal   r1e_byp_l_q                   :   std_ulogic; 
+signal   r0_byp_sel                    :   std_ulogic_vector(0 to 1);
+signal   r1_byp_sel                    :   std_ulogic_vector(0 to 1);
+
+signal unused           : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+   tilo      <= '0';
+   tihi      <= '1';
+   zeross    <= (0 to 3  => '0');
+
+       reset       <= nclk.sreset;
+       correct_clk <= nclk.clk;
+       clk2x       <= nclk.clk2x;
+
+       reset_hi    <=     reset;
+       reset_lo    <= not reset_q after 1 ns ;
+
+
+   flipper_d <= not flipper_q;
+
+   slatch: process (correct_clk,reset) begin
+   if rising_edge(correct_clk) then
+    if (reset = '1') then
+      w0l_en_q    <= '0';
+      r1e_addr_q  <= (others => '0');
+      r0e_byp_e_q  <= '0';
+      r0e_byp_l_q  <= '0';
+      r1e_byp_e_q  <= '0';
+      r1e_byp_l_q  <= '0';
+
+    else
+      w0e_data_q   <= w0e_data_func;
+      w0l_data_q   <= w0l_data_func;
+      w0l_en_q     <= w0l_en_func;
+      w0l_addr_q   <= w0l_addr_func;
+      r1e_addr_q   <= r1e_addr_func;
+      r0e_byp_e_q  <= r0e_byp_e;
+      r0e_byp_l_q  <= r0e_byp_l;
+      r1e_byp_e_q  <= r1e_byp_e;
+      r1e_byp_l_q  <= r1e_byp_l;
+
+    end if;
+   end if;
+   end process;
+
+   flatch: process (clk2x,reset_lo) begin
+  if clk2x'event and clk2x = '1' then
+    if (reset_lo = '0') then
+      flipper_q  <= '0';
+
+    else
+      flipper_q    <= flipper_d;
+      doutb0_q     <= tconv(doutb0);
+
+    end if;
+   end if;
+   end process;
+
+   rlatch: process (correct_clk) begin
+    if(rising_edge(correct_clk)) then
+      reset_q   <= reset_hi;
+      sinit0_q  <= reset_hi;
+      sinit1_q  <= reset_hi;
+    end if;
+   end process;
+
+
+   addra(0)       <= '0';
+   addra(1 to 8)  <= (tconv((w0e_addr_func and (0 to  7 => flipper_q)) or (w0l_addr_q and (0 to  7 => not flipper_q))))  after 1 ns ; 
+   weaf           <= ((      w0e_en_func   and             flipper_q)  or (  w0l_en_q and             not  flipper_q))   after 1 ns;
+   dinfa          <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q))))  after 1 ns;
+ 
+   dinfb          <= (others => '0');
+   addrb0(0)      <= '0';
+   addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q  and (0 to 7 => not flipper_q)))) after 1 ns ;  
+
+   r0_byp_sel <= r0e_byp_e & r0e_byp_l;
+   with r0_byp_sel select 
+   r0e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     doutb0_q   when others;
+
+   r1_byp_sel <= r1e_byp_e & r1e_byp_l;
+   with r1_byp_sel select 
+   r1e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     tconv(doutb0) when others;
+
+
+U0 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(0 to 31),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(0 to 31),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit0_q,
+		SSRB  => sinit0_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+U1 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(32 to 63),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(32 to 63),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+doutb0(64 to 77)     <= doutb0_par(64 to 77);
+dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0');
+
+U2 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0_par(64 to 95),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa0_par(64 to 95),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+r_scan_out <= '0';
+w_scan_out <= '0';
+time_scan_out <= '0';
+obs0_scan_out <= '0';
+obs1_scan_out <= '0';
+
+bo_pc_failout <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95))
+                     & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en
+                     & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc
+                     & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                     & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0
+                     & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0
+                     & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0
+                     & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in
+                     & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist
+                     & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist
+                     & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist
+                     & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate;
+
+end architecture tri_144x78_2r2w;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w_eco.vhdl

@@ -0,0 +1,412 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use ibm.std_ulogic_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+
+entity tri_144x78_2r2w_eco is
+generic(
+   expand_type                         :     integer :=  1);
+port (
+   vdd                            :inout power_logic;    
+   gnd                            :inout power_logic;    
+   nclk                           :in   clk_logic;                 
+   abist_en                       :in   std_ulogic;  
+   abist_raw_dc_b                 :in   std_ulogic;  
+   r0e_abist_comp_en              :in   std_ulogic;  
+   r1e_abist_comp_en              :in   std_ulogic;  
+   lbist_en                      :in   std_ulogic;  
+
+   lcb_act_dis_dc                 :in   std_ulogic; 
+   lcb_clkoff_dc_b                :in   std_ulogic_vector(0 to 1);
+   lcb_d_mode_dc                  :in   std_ulogic;
+   lcb_delay_lclkr_dc             :in   std_ulogic_vector(0 to 9); 
+   lcb_fce_0                      :in   std_ulogic; 
+   lcb_mpw1_dc_b                  :in   std_ulogic_vector(1 to 9); 
+   lcb_mpw2_dc_b                  :in   std_ulogic; 
+   lcb_scan_diag_dc               :in   std_ulogic; 
+   lcb_scan_dis_dc_b              :in   std_ulogic; 
+   lcb_sg_0                       :in   std_ulogic; 
+   lcb_time_sg_0                  :in   std_ulogic;
+
+   lcb_obs0_sg_0                  :in   std_ulogic; 
+   lcb_obs1_sg_0                  :in   std_ulogic; 
+   lcb_obs0_sl_thold_0            :in   std_ulogic; 
+   lcb_obs1_sl_thold_0            :in   std_ulogic; 
+
+   lcb_abst_sl_thold_0            :in   std_ulogic;  
+   lcb_time_sl_thold_0            :in   std_ulogic; 
+   lcb_ary_nsl_thold_0            :in   std_ulogic;  
+
+   r_scan_in                      :in   std_ulogic;                 
+   r_scan_out                     :out  std_ulogic;   
+   w_scan_in                      :in   std_ulogic;                 
+   w_scan_out                     :out  std_ulogic;   
+   time_scan_in                   :in   std_ulogic; 
+   time_scan_out                  :out  std_ulogic; 
+   obs0_scan_in                   :in   std_ulogic; 
+   obs0_scan_out                  :out  std_ulogic; 
+   obs1_scan_in                   :in   std_ulogic; 
+   obs1_scan_out                  :out  std_ulogic; 
+
+   lcb_bolt_sl_thold_0            :in   std_ulogic;
+   pc_bo_enable_2                 :in   std_ulogic; 
+   pc_bo_reset                    :in   std_ulogic; 
+   pc_bo_unload                   :in   std_ulogic;
+   pc_bo_load                     :in   std_ulogic;
+   pc_bo_shdata                   :in   std_ulogic; 
+   pc_bo_select                   :in   std_ulogic; 
+   bo_pc_failout                  :out  std_ulogic; 
+   bo_pc_diagloop                 :out  std_ulogic;
+   tri_lcb_mpw1_dc_b              :in    std_ulogic;
+   tri_lcb_mpw2_dc_b              :in    std_ulogic;
+   tri_lcb_delay_lclkr_dc         :in    std_ulogic;
+   tri_lcb_clkoff_dc_b            :in    std_ulogic;
+   tri_lcb_act_dis_dc             :in    std_ulogic;
+
+   r0e_act                        :in   std_ulogic;                 
+   r0e_en_func                    :in   std_ulogic;                 
+   r0e_en_abist                   :in   std_ulogic;                 
+   r0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r0e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r0e_data_out                   :out  std_ulogic_vector(0 to 77); 
+   r0e_byp_e                      :in   std_ulogic; 
+   r0e_byp_l                      :in   std_ulogic; 
+   r0e_byp_r                      :in   std_ulogic;
+   r0e_sel_lbist                  :in   std_ulogic; 
+
+   r1e_act                        :in   std_ulogic;                 
+   r1e_en_func                    :in   std_ulogic;                 
+   r1e_en_abist                   :in   std_ulogic;                 
+   r1e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r1e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r1e_data_out                   :out  std_ulogic_vector(0 to 77);
+   r1e_byp_e                      :in   std_ulogic; 
+   r1e_byp_l                      :in   std_ulogic; 
+   r1e_byp_r                      :in   std_ulogic;
+   r1e_sel_lbist                  :in   std_ulogic; 
+
+   w0e_act                        :in   std_ulogic;                 
+   w0e_en_func                    :in   std_ulogic;                 
+   w0e_en_abist                   :in   std_ulogic;                 
+   w0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0e_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0e_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0e_data_abist                 :in   std_ulogic_vector(0 to 3);
+
+   w0l_act                        :in   std_ulogic;                 
+   w0l_en_func                    :in   std_ulogic;                 
+   w0l_en_abist                   :in   std_ulogic;                 
+   w0l_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0l_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0l_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0l_data_abist                 :in   std_ulogic_vector(0 to 3) );
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity   tri_144x78_2r2w_eco;
+architecture tri_144x78_2r2w_eco of tri_144x78_2r2w_eco is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal  tilo                           : std_ulogic;
+signal  tihi                           : std_ulogic;
+signal  zeross                         : std_logic_vector(0 to 3); 
+
+signal  correct_clk                    : std_ulogic;
+signal  clk2x                          : std_ulogic;
+signal  reset                          : std_ulogic;
+signal  reset_hi                       : std_ulogic;
+signal  reset_lo                       : std_ulogic;
+signal  reset_q                        : std_ulogic;
+signal  sinit0_q        : std_logic;
+signal  sinit1_q        : std_logic;
+signal  flipper_d                      : std_ulogic;
+signal  flipper_q                      : std_ulogic;
+
+signal  doutb0                         : std_logic_vector(0 to 77);
+signal  doutb0_q                       : std_ulogic_vector(0 to 77);
+signal dinfa0_par                      : std_logic_vector(64 to 95);
+signal doutb0_par                      : std_logic_vector(64 to 95);
+signal  weaf                           : std_logic;
+signal  addra                          : std_logic_vector(0 to 8); 
+signal  addrb0                         : std_logic_vector(0 to 8); 
+signal  dinfa                          : std_logic_vector(0 to 77); 
+signal  dinfb                          : std_logic_vector(0 to 31); 
+
+signal  w0e_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_en_q                       : std_ulogic;
+signal  w0l_addr_q                     : std_ulogic_vector(0 to 7);
+signal  r1e_addr_q                     : std_ulogic_vector(0 to 7);
+
+signal   r0e_byp_e_q                   :   std_ulogic; 
+signal   r0e_byp_l_q                   :   std_ulogic; 
+signal   r1e_byp_e_q                   :   std_ulogic; 
+signal   r1e_byp_l_q                   :   std_ulogic; 
+signal   r0_byp_sel                    :   std_ulogic_vector(0 to 1);
+signal   r1_byp_sel                    :   std_ulogic_vector(0 to 1);
+
+signal unused           : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+   tilo      <= '0';
+   tihi      <= '1';
+   zeross    <= (0 to 3  => '0');
+
+       reset       <= nclk.sreset;
+       correct_clk <= nclk.clk;
+       clk2x       <= nclk.clk2x;
+
+       reset_hi    <=     reset;
+       reset_lo    <= not reset_q after 1 ns ;
+
+
+   flipper_d <= not flipper_q;
+
+   slatch: process (correct_clk,reset) begin
+   if rising_edge(correct_clk) then
+    if (reset = '1') then
+      w0l_en_q    <= '0';
+      r1e_addr_q  <= (others => '0');
+      r0e_byp_e_q  <= '0';
+      r0e_byp_l_q  <= '0';
+      r1e_byp_e_q  <= '0';
+      r1e_byp_l_q  <= '0';
+
+    else
+      w0e_data_q   <= w0e_data_func;
+      w0l_data_q   <= w0l_data_func;
+      w0l_en_q     <= w0l_en_func;
+      w0l_addr_q   <= w0l_addr_func;
+      r1e_addr_q   <= r1e_addr_func;
+      r0e_byp_e_q  <= r0e_byp_e;
+      r0e_byp_l_q  <= r0e_byp_l;
+      r1e_byp_e_q  <= r1e_byp_e;
+      r1e_byp_l_q  <= r1e_byp_l;
+
+    end if;
+   end if;
+   end process;
+
+   flatch: process (clk2x,reset_lo) begin
+  if clk2x'event and clk2x = '1' then
+    if (reset_lo = '0') then
+      flipper_q  <= '0';
+
+    else
+      flipper_q    <= flipper_d;
+      doutb0_q     <= tconv(doutb0);
+
+    end if;
+   end if;
+   end process;
+
+   rlatch: process (correct_clk) begin
+    if(rising_edge(correct_clk)) then
+      reset_q   <= reset_hi;
+      sinit0_q  <= reset_hi;
+      sinit1_q  <= reset_hi;
+    end if;
+   end process;
+
+
+   addra(0)       <= '0';
+   addra(1 to 8)  <= (tconv((w0e_addr_func and (0 to  7 => flipper_q)) or (w0l_addr_q and (0 to  7 => not flipper_q))))  after 1 ns ; 
+   weaf           <= ((      w0e_en_func   and             flipper_q)  or (  w0l_en_q and             not  flipper_q))   after 1 ns;
+   dinfa          <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q))))  after 1 ns;
+ 
+   dinfb          <= (others => '0');
+   addrb0(0)      <= '0';
+   addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q  and (0 to 7 => not flipper_q)))) after 1 ns ;  
+
+   r0_byp_sel <= r0e_byp_e & r0e_byp_l;
+   with r0_byp_sel select 
+   r0e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     doutb0_q   when others;
+
+   r1_byp_sel <= r1e_byp_e & r1e_byp_l;
+   with r1_byp_sel select 
+   r1e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     tconv(doutb0) when others;
+
+
+U0 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(0 to 31),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(0 to 31),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit0_q,
+		SSRB  => sinit0_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+U1 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(32 to 63),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(32 to 63),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+doutb0(64 to 77)     <= doutb0_par(64 to 77);
+dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0');
+
+U2 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0_par(64 to 95),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa0_par(64 to 95),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+r_scan_out <= '0';
+w_scan_out <= '0';
+time_scan_out <= '0';
+obs0_scan_out <= '0';
+obs1_scan_out <= '0';
+
+bo_pc_failout <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95))
+                     & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en
+                     & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc
+                     & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                     & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0
+                     & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0
+                     & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0
+                     & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in
+                     & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist
+                     & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist
+                     & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist
+                     & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate;
+
+end architecture tri_144x78_2r2w_eco;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_256x162_4w_0.vhdl

@@ -0,0 +1,359 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support;
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_256x162_4w_0 is
+  generic (addressable_ports : positive := 256; 
+           addressbus_width : positive := 8;    
+           port_bitwidth : positive := 162;     
+           ways : positive := 4;                
+           expand_type : integer := 1);         
+  port (
+    gnd               : inout power_logic;
+    vdd               : inout power_logic;
+    vcs               : inout power_logic;
+    nclk                        : in  clk_logic;
+    ccflush_dc                  : in  std_ulogic;
+    lcb_clkoff_dc_b             : in  std_ulogic;
+    lcb_d_mode_dc               : in  std_ulogic;
+    lcb_act_dis_dc              : in  std_ulogic;
+    lcb_ary_nsl_thold_0         : in  std_ulogic;
+    lcb_sg_1                    : in  std_ulogic;
+    lcb_abst_sl_thold_0         : in  std_ulogic;
+    scan_diag_dc                : in  std_ulogic;
+    scan_dis_dc_b               : in  std_ulogic;
+    abst_scan_in                : in  std_ulogic_vector(0 to 1);
+    abst_scan_out               : out std_ulogic_vector(0 to 1);
+    lcb_delay_lclkr_np_dc       : in  std_ulogic;
+    ctrl_lcb_delay_lclkr_np_dc  : in  std_ulogic;
+    dibw_lcb_delay_lclkr_np_dc  : in  std_ulogic;
+    ctrl_lcb_mpw1_np_dc_b       : in  std_ulogic;
+    dibw_lcb_mpw1_np_dc_b       : in  std_ulogic;
+    lcb_mpw1_pp_dc_b            : in  std_ulogic;
+    lcb_mpw1_2_pp_dc_b          : in  std_ulogic;
+    aodo_lcb_delay_lclkr_dc     : in  std_ulogic;
+    aodo_lcb_mpw1_dc_b          : in  std_ulogic;
+    aodo_lcb_mpw2_dc_b          : in  std_ulogic;
+    lcb_time_sg_0               : in    std_ulogic;
+    lcb_time_sl_thold_0         : in    std_ulogic;
+    time_scan_in                : in    std_ulogic;
+    time_scan_out               : out   std_ulogic;
+    bitw_abist                  : in    std_ulogic_vector(0 to 1);
+    lcb_repr_sl_thold_0         : in    std_ulogic;
+    lcb_repr_sg_0               : in    std_ulogic;
+    repr_scan_in                : in    std_ulogic;
+    repr_scan_out               : out   std_ulogic;
+    tc_lbist_ary_wrt_thru_dc    : in    std_ulogic;
+    abist_en_1                  : in    std_ulogic;
+    din_abist                   : in    std_ulogic_vector(0 to 3);
+    abist_cmp_en                : in    std_ulogic;
+    abist_raw_b_dc              : in    std_ulogic;
+    data_cmp_abist              : in    std_ulogic_vector(0 to 3);
+    addr_abist                  : in    std_ulogic_vector(0 to (addressbus_width-1));
+    r_wb_abist                  : in    std_ulogic;
+    write_thru_en_dc            : in    std_ulogic;
+    lcb_bolt_sl_thold_0         : in    std_ulogic; 
+    pc_bo_enable_2              : in    std_ulogic; 
+    pc_bo_reset                 : in    std_ulogic; 
+    pc_bo_unload                : in    std_ulogic;
+    pc_bo_repair                : in    std_ulogic; 
+    pc_bo_shdata                : in    std_ulogic; 
+    pc_bo_select                : in    std_ulogic_vector(0 to 1); 
+    bo_pc_failout               : out   std_ulogic_vector(0 to 1); 
+    bo_pc_diagloop              : out   std_ulogic_vector(0 to 1);
+    tri_lcb_mpw1_dc_b           : in    std_ulogic;
+    tri_lcb_mpw2_dc_b           : in    std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in    std_ulogic;
+    tri_lcb_clkoff_dc_b         : in    std_ulogic;
+    tri_lcb_act_dis_dc          : in    std_ulogic;
+    read_act          : in std_ulogic;
+    write_enable      : in std_ulogic;
+    write_way         : in std_ulogic_vector (0 to (ways-1));
+    addr              : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in           : in std_ulogic_vector (0 to (port_bitwidth-1));
+    data_out          : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_256x162_4w_0;
+
+architecture tri_256x162_4w_0 of tri_256x162_4w_0 is
+
+constant wga_base_width : integer := 324;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+
+
+type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal act                : std_ulogic;
+      signal addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal write_way_l2       : std_ulogic_vector (0 TO write_way'right);
+      signal write_enable_d     : std_ulogic;
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      act <= read_act or or_reduce(write_way);
+
+      addr_latch: tri_rlmreg_p
+        generic map (width => addr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr,
+                  dout        => addr_l2 );
+
+      write_way_latch: tri_rlmreg_p
+        generic map (width => write_way'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => write_way,
+                  dout        => write_way_l2 );
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= act and write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and 
+                                          write_way_l2(w)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out     <= "00";
+      time_scan_out     <= '0';
+      repr_scan_out     <= '0';
+
+      bo_pc_failout     <= "00";
+      bo_pc_diagloop    <= "00";
+
+  end generate um;
+  -- synopsys translate_on
+
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+        -- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+        -- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal ramb_data_in       : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+      signal ramb_data_out      : RAMB_DATA_ARRAY(0 to ways-1);
+      signal ramb_addr          : std_logic_vector(0 to ramb_base_addr - 1);
+
+      signal act                : std_ulogic_vector(0 to ways-1);
+      signal write              : std_ulogic_vector(0 to ways-1);
+      signal tidn               : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      add0: if (addressbus_width < ramb_base_addr) generate
+      begin
+        ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr );
+      end generate;
+      add1: if (addressbus_width >= ramb_base_addr) generate
+      begin
+        ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+      end generate;
+
+      din: for i in ramb_data_in'range generate
+      begin
+        R0: if(i <  port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate;
+        R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate;
+      end generate;
+
+      aw: for w in 0 to ways-1 generate begin
+        act(w) <= read_act or write_way(w);
+        write(w) <= write_enable and write_way(w);
+
+        ax: for x in 0 to (ramb_width_mult - 1) generate begin
+          arr: RAMB16_S36_S36
+            -- pragma translate_off
+            generic map(
+                        sim_collision_check => "none")
+            -- pragma translate_on
+            port map(
+		DOA   => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DOB   => open,
+		DOPA  => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DOPB  => open,
+		ADDRA => ramb_addr,
+		ADDRB => ramb_addr,
+		CLKA  => nclk.clk,
+		CLKB  => tidn,
+		DIA   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIB   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIPA  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DIPB  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		ENA   => act(w),
+		ENB   => tidn,
+		SSRA  => nclk.sreset,
+		SSRB  => tidn,
+		WEA   => write(w),
+		WEB   => tidn
+	  );
+
+        end generate ax;
+
+        data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) );
+
+      end generate aw;
+
+      abst_scan_out     <= "00";
+      time_scan_out     <= '0';
+      repr_scan_out     <= '0';
+
+      bo_pc_failout     <= "00";
+      bo_pc_diagloop    <= "00";
+
+      unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & std_ulogic_vector(ramb_data_out(1)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & std_ulogic_vector(ramb_data_out(2)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & std_ulogic_vector(ramb_data_out(3)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & ccflush_dc & lcb_clkoff_dc_b & lcb_d_mode_dc & lcb_act_dis_dc
+                       & scan_dis_dc_b & scan_diag_dc & bitw_abist
+                       & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0
+                       & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 
+                       & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc 
+                       & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist 
+                       & addr_abist & r_wb_abist & write_thru_en_dc & abst_scan_in & time_scan_in & repr_scan_in
+                       & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc
+                       & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b
+                       & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b
+                       & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                       & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+  end generate a;
+
+end tri_256x162_4w_0;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_32x35_8w_1r1w.vhdl

@@ -0,0 +1,578 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm;  use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_32x35_8w_1r1w is
+  generic (addressable_ports : positive := 32; 
+           addressbus_width : positive := 5;   
+           port_bitwidth : positive := 35;     
+           ways : positive := 8;                
+           expand_type : integer := 1);         
+  port (
+    gnd               : inout power_logic;
+    vdd               : inout power_logic;
+    vcs               : inout power_logic;
+    nclk              : in clk_logic;
+    rd0_act           : in std_ulogic;
+    sg_0              : in std_ulogic;
+    abst_slp_sl_thold_0 : in std_ulogic;
+    ary_slp_nsl_thold_0 : in std_ulogic;
+    time_sl_thold_0   : in std_ulogic;
+    repr_sl_thold_0   : in std_ulogic;
+    clkoff_dc_b       : in std_ulogic;
+    ccflush_dc        : in std_ulogic;
+    scan_dis_dc_b     : in std_ulogic;
+    scan_diag_dc      : in std_ulogic;
+    d_mode_dc         : in std_ulogic;
+    mpw1_dc_b         : in std_ulogic_vector(0 to 4);
+    mpw2_dc_b         : in std_ulogic;
+    delay_lclkr_dc    : in std_ulogic_vector(0 to 4);
+    wr_abst_act       : in std_ulogic;
+    rd0_abst_act      : in std_ulogic;
+    abist_di          : in std_ulogic_vector(0 to 3);
+    abist_bw_odd      : in std_ulogic;
+    abist_bw_even     : in std_ulogic;
+    abist_wr_adr      : in std_ulogic_vector(0 to 4);
+    abist_rd0_adr     : in std_ulogic_vector(0 to 4);
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_ena_1                 : in std_ulogic;
+    abist_g8t_rd0_comp_ena      : in std_ulogic;
+    abist_raw_dc_b              : in std_ulogic;
+    obs0_abist_cmp              : in std_ulogic_vector(0 to 3);
+    abst_scan_in      : in std_ulogic;
+    time_scan_in      : in std_ulogic;
+    repr_scan_in      : in std_ulogic;
+    abst_scan_out     : out std_ulogic;
+    time_scan_out     : out std_ulogic;
+    repr_scan_out     : out std_ulogic;
+    lcb_bolt_sl_thold_0         : in std_ulogic;
+    pc_bo_enable_2              : in std_ulogic; 
+    pc_bo_reset                 : in std_ulogic; 
+    pc_bo_unload                : in std_ulogic; 
+    pc_bo_repair                : in std_ulogic; 
+    pc_bo_shdata                : in std_ulogic; 
+    pc_bo_select                : in std_ulogic_vector(0 to 3); 
+    bo_pc_failout               : out std_ulogic_vector(0 to 3); 
+    bo_pc_diagloop              : out std_ulogic_vector(0 to 3);
+    tri_lcb_mpw1_dc_b           : in  std_ulogic;
+    tri_lcb_mpw2_dc_b           : in  std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in  std_ulogic;
+    tri_lcb_clkoff_dc_b         : in  std_ulogic;
+    tri_lcb_act_dis_dc          : in  std_ulogic;
+    write_enable      : in std_ulogic_vector (0 to ((port_bitwidth*ways-1)/(port_bitwidth*2)));
+    way               : in std_ulogic_vector (0 to (ways-1));
+    addr_wr           : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in           : in std_ulogic_vector (0 to (port_bitwidth-1));
+    addr_rd_01        : in std_ulogic_vector (0 to (addressbus_width-1));
+    addr_rd_23        : in std_ulogic_vector (0 to (addressbus_width-1));
+    addr_rd_45        : in std_ulogic_vector (0 to (addressbus_width-1));
+    addr_rd_67        : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_out          : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_32x35_8w_1r1w;
+
+architecture tri_32x35_8w_1r1w of tri_32x35_8w_1r1w is
+
+constant wga_base_width : integer := 70;
+constant wga_base_addr  : integer := 5;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+
+
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal addr_rd_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal addr_wr_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal way_l2             : std_ulogic_vector (0 TO way'right);
+      signal write_enable_d     : std_ulogic_vector(0 to wga_width_mult-1);
+      signal write_enable_l2    : std_ulogic_vector(0 to wga_width_mult-1);
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal act                : std_ulogic;
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      act <= or_reduce(write_enable) or rd0_act;
+
+      addr_rd_latch: tri_rlmreg_p
+        generic map (width => addr_rd_01'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr_rd_01,
+                  dout        => addr_rd_l2 );
+
+      addr_wr_latch: tri_rlmreg_p
+        generic map (width => addr_wr'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr_wr,
+                  dout        => addr_wr_l2 );
+
+      way_latch: tri_rlmreg_p
+        generic map (width => way'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => way,
+                  dout        => way_l2 );
+
+      write_enable_latch: tri_rlmreg_p
+        generic map (width => wga_width_mult, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( or_reduce(write_enable_l2) and addr_wr_l2 = tconv(y, addressbus_width) and 
+                                          way_l2(w)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_rd_l2)*port_bitwidth*ways to tconv(addr_rd_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out <= tidn;
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= "0000";
+      bo_pc_diagloop <= "0000";
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+        -- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+        -- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal array_wr_data      : std_logic_vector(0 to port_bitwidth - 1);
+      signal ramb_data_in       : std_logic_vector(0 to 35);
+      signal ramb_data_outA     : std_logic_vector(0 to 35);
+      signal ramb_data_outB     : std_logic_vector(0 to 35);
+      signal ramb_data_outC     : std_logic_vector(0 to 35);
+      signal ramb_data_outD     : std_logic_vector(0 to 35);
+      signal ramb_data_outE     : std_logic_vector(0 to 35);
+      signal ramb_data_outF     : std_logic_vector(0 to 35);
+      signal ramb_data_outG     : std_logic_vector(0 to 35);
+      signal ramb_data_outH     : std_logic_vector(0 to 35);
+      signal ramb_addr_wr       : std_logic_vector(0 to ramb_base_addr - 1);
+      signal ramb_addr_rd       : std_logic_vector(0 to ramb_base_addr - 1);
+      signal data_outA          : std_ulogic_vector(0 to 35);
+      signal data_outB          : std_ulogic_vector(0 to 35);
+      signal data_outC          : std_ulogic_vector(0 to 35);
+      signal data_outD          : std_ulogic_vector(0 to 35);
+      signal data_outE          : std_ulogic_vector(0 to 35);
+      signal data_outF          : std_ulogic_vector(0 to 35);
+      signal data_outG          : std_ulogic_vector(0 to 35);
+      signal data_outH          : std_ulogic_vector(0 to 35);
+
+      signal rd_addr            : std_ulogic_vector(0 to ramb_base_addr - 1);
+      signal wr_addr            : std_ulogic_vector(0 to ramb_base_addr - 1);
+      signal write_enable_wA    : std_ulogic;
+      signal write_enable_wB    : std_ulogic;
+      signal write_enable_wC    : std_ulogic;
+      signal write_enable_wD    : std_ulogic;
+      signal write_enable_wE    : std_ulogic;
+      signal write_enable_wF    : std_ulogic;
+      signal write_enable_wG    : std_ulogic;
+      signal write_enable_wH    : std_ulogic;
+      signal tidn               : std_logic_vector(0 to 35);
+      signal act                : std_ulogic;
+      signal wen                : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= (others=>'0');
+
+      wen <= or_reduce(write_enable);
+      act <= rd0_act or wen;
+
+      array_wr_data <= tconv(data_in);
+      addr_calc : for t in 0 to 35 generate begin
+            R0 : if(t < 35 - (port_bitwidth-1))  generate begin ramb_data_in(t) <= '0';                                       end generate;
+            R1 : if(t >= 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= array_wr_data(t-(35-(port_bitwidth-1)));   end generate;
+      end generate addr_calc;
+
+      write_enable_wA <= wen and way(0);
+      write_enable_wB <= wen and way(1);
+      write_enable_wC <= wen and way(2);
+      write_enable_wD <= wen and way(3);
+      write_enable_wE <= wen and way(4);
+      write_enable_wF <= wen and way(5);
+      write_enable_wG <= wen and way(6);
+      write_enable_wH <= wen and way(7);      
+
+      rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin
+            R0 : if(t < ramb_base_addr-addressbus_width) generate begin
+                  rd_addr(t) <= '0';
+                  wr_addr(t) <= '0';
+                 end generate;
+            R1 : if(t >= ramb_base_addr-addressbus_width) generate begin
+                  rd_addr(t) <= addr_rd_01(t-(ramb_base_addr-addressbus_width));
+                  wr_addr(t) <= addr_wr(t-(ramb_base_addr-addressbus_width));
+                 end generate;
+      end generate rambAddrCalc;
+
+      ramb_addr_wr <= tconv(wr_addr);
+      ramb_addr_rd <= tconv(rd_addr);
+
+      data_outA <= tconv(ramb_data_outA);
+      data_outB <= tconv(ramb_data_outB);
+      data_outC <= tconv(ramb_data_outC);
+      data_outD <= tconv(ramb_data_outD);
+      data_outE <= tconv(ramb_data_outE);
+      data_outF <= tconv(ramb_data_outF);
+      data_outG <= tconv(ramb_data_outG);
+      data_outH <= tconv(ramb_data_outH);
+
+      data_out <= data_outA((35-(port_bitwidth-1)) to 35) & data_outB((35-(port_bitwidth-1)) to 35) &
+                  data_outC((35-(port_bitwidth-1)) to 35) & data_outD((35-(port_bitwidth-1)) to 35) &
+                  data_outE((35-(port_bitwidth-1)) to 35) & data_outF((35-(port_bitwidth-1)) to 35) &
+                  data_outG((35-(port_bitwidth-1)) to 35) & data_outH((35-(port_bitwidth-1)) to 35);
+
+      arr0_A: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outA(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outA(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wA
+	  );
+
+      arr1_B: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outB(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outB(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wB
+	  );
+
+      arr2_C: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outC(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outC(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wC
+	  );
+
+      arr3_D: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outD(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outD(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wD
+	  );
+
+      arr4_E: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outE(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outE(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wE
+	  );
+
+      arr5_F: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outF(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outF(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wF
+	  );
+
+      arr6_G: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outG(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outG(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wG
+	  );
+
+      arr7_H: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outH(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outH(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wH
+	  );
+
+      abst_scan_out <= tidn(0);
+      time_scan_out <= tidn(0);
+      repr_scan_out <= tidn(0);
+
+      bo_pc_failout <= "0000";
+      bo_pc_diagloop <= "0000";
+
+      unused <= or_reduce( data_outA(0) & data_outB(0) & data_outC(0) & data_outD(0)
+                           & data_outE(0) & data_outF(0) & data_outG(0) & data_outH(0)
+                           & sg_0 & abst_slp_sl_thold_0 & ary_slp_nsl_thold_0
+                           & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc
+                           & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b
+                           & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di
+                           & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                           & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                           & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in
+                           & repr_scan_in & addr_rd_23 & addr_rd_45 & addr_rd_67
+                           & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                           & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                           & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                           & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+  end generate a;
+
+end tri_32x35_8w_1r1w;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_512x288_9.vhdl

@@ -0,0 +1,762 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_512x288_9 is
+  generic (addressable_ports : positive := 512; 
+           addressbus_width : positive := 6;    
+           port_bitwidth : positive := 288;     
+           bit_write_type : positive := 9;  
+           ways : positive := 1;        
+           expand_type : integer := 1);         
+  port (
+    gnd               : inout power_logic;
+    vdd               : inout power_logic;
+    vcs               : inout power_logic;
+    nclk              : in clk_logic;
+    act               : in std_ulogic;
+    sg_0              : in std_ulogic;
+    sg_1              : in std_ulogic;
+    ary_nsl_thold_0   : in std_ulogic;
+    abst_sl_thold_0   : in std_ulogic;
+    time_sl_thold_0   : in std_ulogic;
+    repr_sl_thold_0   : in std_ulogic;
+    clkoff_dc_b       : in std_ulogic;
+    ccflush_dc        : in std_ulogic;
+    scan_dis_dc_b     : in std_ulogic;
+    scan_diag_dc      : in std_ulogic;
+    d_mode_dc         : in std_ulogic;
+    act_dis_dc        : in std_ulogic;
+    lcb_delay_lclkr_np_dc       : in std_ulogic;
+    ctrl_lcb_delay_lclkr_np_dc  : in std_ulogic;
+    dibw_lcb_delay_lclkr_np_dc  : in std_ulogic;
+    ctrl_lcb_mpw1_np_dc_b       : in std_ulogic;
+    dibw_lcb_mpw1_np_dc_b       : in std_ulogic;
+    lcb_mpw1_pp_dc_b            : in std_ulogic;
+    lcb_mpw1_2_pp_dc_b          : in std_ulogic;
+    aodo_lcb_delay_lclkr_dc     : in std_ulogic;
+    aodo_lcb_mpw1_dc_b          : in std_ulogic;
+    aodo_lcb_mpw2_dc_b          : in std_ulogic;
+    bitw_abist                  : in std_ulogic_vector(0 to 1);
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_en_1                  : in std_ulogic;
+    din_abist                   : in std_ulogic_vector(0 to 3);
+    abist_cmp_en                : in std_ulogic;
+    abist_raw_b_dc              : in std_ulogic;
+    data_cmp_abist              : in std_ulogic_vector(0 to 3);
+    addr_abist                  : in std_ulogic_vector(0 to 8);
+    r_wb_abist                  : in std_ulogic;
+    abst_scan_in      : in std_ulogic_vector(0 to 1);
+    time_scan_in      : in std_ulogic;
+    repr_scan_in      : in std_ulogic;
+    abst_scan_out     : out std_ulogic_vector(0 to 1);
+    time_scan_out     : out std_ulogic;
+    repr_scan_out     : out std_ulogic;
+    lcb_bolt_sl_thold_0         : in std_ulogic; 
+    pc_bo_enable_2              : in std_ulogic; 
+    pc_bo_reset                 : in std_ulogic; 
+    pc_bo_unload                : in std_ulogic;
+    pc_bo_repair                : in std_ulogic; 
+    pc_bo_shdata                : in std_ulogic; 
+    pc_bo_select                : in std_ulogic_vector(0 to 1); 
+    bo_pc_failout               : out std_ulogic_vector(0 to 1); 
+    bo_pc_diagloop              : out std_ulogic_vector(0 to 1);
+    tri_lcb_mpw1_dc_b           : in  std_ulogic;
+    tri_lcb_mpw2_dc_b           : in  std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in  std_ulogic;
+    tri_lcb_clkoff_dc_b         : in  std_ulogic;
+    tri_lcb_act_dis_dc          : in  std_ulogic;
+    write_enable      : in std_ulogic;
+    bw                : in std_ulogic_vector (0 to (port_bitwidth-1));
+    arr_up_addr       : in std_ulogic_vector (0 to 2);
+    addr              : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in           : in std_ulogic_vector (0 to (port_bitwidth-1));
+    data_out          : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_512x288_9;
+
+architecture tri_512x288_9 of tri_512x288_9 is
+
+
+
+
+constant ramb_base_addr  : integer := 11;
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal addr_l2            : std_ulogic_vector(0 TO addressbus_width-1);
+      signal bw_l2              : std_ulogic_vector(0 TO bw'right);
+      signal write_enable_d     : std_ulogic;
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      addr_latch: tri_rlmreg_p
+        generic map (width => addr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr,
+                  dout        => addr_l2 );
+
+      bw_latch: tri_rlmreg_p
+        generic map (width => bw'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => bw,
+                  dout        => bw_l2 );
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= act and write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and bw_l2(x/bit_write_type) ) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out <= (others=>'0');
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= (others=>'0');
+      bo_pc_diagloop <= (others=>'0');
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+      component RAMB16_S9_S9
+      -- pragma translate_off
+	generic
+	(
+		SIM_COLLISION_CHECK : string := "none"); 
+      -- pragma translate_on
+	port
+	(
+		DOA : out std_logic_vector(7 downto 0);
+		DOB : out std_logic_vector(7 downto 0);
+		DOPA : out std_logic_vector(0 downto 0);
+		DOPB : out std_logic_vector(0 downto 0);
+		ADDRA : in std_logic_vector(10 downto 0);
+		ADDRB : in std_logic_vector(10 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(7 downto 0);
+		DIB : in std_logic_vector(7 downto 0);
+		DIPA : in std_logic_vector(0 downto 0);
+		DIPB : in std_logic_vector(0 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      constant addresswidth     : integer := addressbus_width+3+1;
+      signal arr_data_in        : std_logic_vector(0 to 287);
+      signal ramb_data_in       : std_logic_vector(0 to 255);
+      signal ramb_parity_in     : std_logic_vector(0 to 31);
+      signal ramb_uh_addr       : std_ulogic_vector(0 to 10);
+      signal ramb_lh_addr       : std_ulogic_vector(0 to 10);
+      signal uh_addr            : std_ulogic_vector(0 to addresswidth-1);
+      signal lh_addr            : std_ulogic_vector(0 to addresswidth-1);
+      signal ramb_data_out      : std_logic_vector(0 to 255);
+      signal ramb_parity_out    : std_logic_vector(0 to 31);
+
+      signal tidn               : std_ulogic;
+      signal wrt_en_wAH         : std_ulogic_vector(0 to 31);
+      signal bitWrt             : std_ulogic_vector(0 to 31);
+      signal rdDataOut          : std_ulogic_vector(0 to 255);
+      signal rdParityOut        : std_ulogic_vector(0 to 31);
+
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      arr_data_in   <= tconv(data_in);
+
+      dWFixUp : for t in 0 to 31 generate begin
+            ramb_data_in((8*t) to (8*t)+7) <= arr_data_in(t+0)   & arr_data_in(t+32)  & arr_data_in(t+64)  & arr_data_in(t+96) &
+                                              arr_data_in(t+144) & arr_data_in(t+176) & arr_data_in(t+208) & arr_data_in(t+240);
+            ramb_parity_in(t)              <= arr_data_in(t+128+(128*(t/16)));
+            bitWrt(t)                      <= bw(t);
+      end generate dWFixUp;
+
+      wrtEn_gen : for t in 0 to 31 generate begin
+            wrt_en_wAH(t) <= write_enable and bitWrt(t);
+      end generate wrtEn_gen;
+
+      uh_addr <= arr_up_addr & addr & '0';
+      lh_addr <= arr_up_addr & addr & '1';
+
+      rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin
+            R0 : if(t < ramb_base_addr-addresswidth) generate begin
+                  ramb_uh_addr(t) <= '0';
+                  ramb_lh_addr(t) <= '0';
+                 end generate;
+            R1 : if(t >= ramb_base_addr-addresswidth) generate begin
+                  ramb_uh_addr(t) <= uh_addr(t-(ramb_base_addr-addresswidth));
+                  ramb_lh_addr(t) <= lh_addr(t-(ramb_base_addr-addresswidth));
+                 end generate;
+      end generate rambAddrCalc;     
+
+      dRFixUp : for t in 0 to 31 generate begin
+            data_out(t+0)                <= rdDataOut((t*8)+0);
+            data_out(t+32)               <= rdDataOut((t*8)+1);
+            data_out(t+64)               <= rdDataOut((t*8)+2);
+            data_out(t+96)               <= rdDataOut((t*8)+3);
+            data_out(t+144)              <= rdDataOut((t*8)+4);
+            data_out(t+176)              <= rdDataOut((t*8)+5);
+            data_out(t+208)              <= rdDataOut((t*8)+6);
+            data_out(t+240)              <= rdDataOut((t*8)+7);
+            data_out(t+128+(128*(t/16))) <= rdParityOut(t);
+      end generate dRFixUp;
+
+      rdDataOut   <= tconv(ramb_data_out);
+      rdParityOut <= tconv(ramb_parity_out);
+
+      arr0: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(0 to 7),
+              DOB   => ramb_data_out(128 to 135),
+              DOPA  => ramb_parity_out(0 to 0),
+              DOPB  => ramb_parity_out(16 to 16),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(0 to 7),
+              DIB   => ramb_data_in(128 to 135),
+              DIPA  => ramb_parity_in(0 to 0),
+              DIPB  => ramb_parity_in(16 to 16),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(0),
+              WEB   => wrt_en_wAH(16)
+	    );
+
+      arr1: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(8 to 15),
+              DOB   => ramb_data_out(136 to 143),
+              DOPA  => ramb_parity_out(1 to 1),
+              DOPB  => ramb_parity_out(17 to 17),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(8 to 15),
+              DIB   => ramb_data_in(136 to 143),
+              DIPA  => ramb_parity_in(1 to 1),
+              DIPB  => ramb_parity_in(17 to 17),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(1),
+              WEB   => wrt_en_wAH(17)
+	    );
+
+      arr2: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(16 to 23),
+              DOB   => ramb_data_out(144 to 151),
+              DOPA  => ramb_parity_out(2 to 2),
+              DOPB  => ramb_parity_out(18 to 18),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(16 to 23),
+              DIB   => ramb_data_in(144 to 151),
+              DIPA  => ramb_parity_in(2 to 2),
+              DIPB  => ramb_parity_in(18 to 18),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(2),
+              WEB   => wrt_en_wAH(18)
+	    );
+
+      arr3: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(24 to 31),
+              DOB   => ramb_data_out(152 to 159),
+              DOPA  => ramb_parity_out(3 to 3),
+              DOPB  => ramb_parity_out(19 to 19),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(24 to 31),
+              DIB   => ramb_data_in(152 to 159),
+              DIPA  => ramb_parity_in(3 to 3),
+              DIPB  => ramb_parity_in(19 to 19),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(3),
+              WEB   => wrt_en_wAH(19)
+	    );
+
+      arr4: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(32 to 39),
+              DOB   => ramb_data_out(160 to 167),
+              DOPA  => ramb_parity_out(4 to 4),
+              DOPB  => ramb_parity_out(20 to 20),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(32 to 39),
+              DIB   => ramb_data_in(160 to 167),
+              DIPA  => ramb_parity_in(4 to 4),
+              DIPB  => ramb_parity_in(20 to 20),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(4),
+              WEB   => wrt_en_wAH(20)
+	    );
+
+      arr5: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(40 to 47),
+              DOB   => ramb_data_out(168 to 175),
+              DOPA  => ramb_parity_out(5 to 5),
+              DOPB  => ramb_parity_out(21 to 21),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(40 to 47),
+              DIB   => ramb_data_in(168 to 175),
+              DIPA  => ramb_parity_in(5 to 5),
+              DIPB  => ramb_parity_in(21 to 21),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(5),
+              WEB   => wrt_en_wAH(21)
+	    );
+
+      arr6: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(48 to 55),
+              DOB   => ramb_data_out(176 to 183),
+              DOPA  => ramb_parity_out(6 to 6),
+              DOPB  => ramb_parity_out(22 to 22),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(48 to 55),
+              DIB   => ramb_data_in(176 to 183),
+              DIPA  => ramb_parity_in(6 to 6),
+              DIPB  => ramb_parity_in(22 to 22),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(6),
+              WEB   => wrt_en_wAH(22)
+	    );
+
+      arr7: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(56 to 63),
+              DOB   => ramb_data_out(184 to 191),
+              DOPA  => ramb_parity_out(7 to 7),
+              DOPB  => ramb_parity_out(23 to 23),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(56 to 63),
+              DIB   => ramb_data_in(184 to 191),
+              DIPA  => ramb_parity_in(7 to 7),
+              DIPB  => ramb_parity_in(23 to 23),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(7),
+              WEB   => wrt_en_wAH(23)
+	    );
+
+      arr8: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(64 to 71),
+              DOB   => ramb_data_out(192 to 199),
+              DOPA  => ramb_parity_out(8 to 8),
+              DOPB  => ramb_parity_out(24 to 24),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(64 to 71),
+              DIB   => ramb_data_in(192 to 199),
+              DIPA  => ramb_parity_in(8 to 8),
+              DIPB  => ramb_parity_in(24 to 24),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(8),
+              WEB   => wrt_en_wAH(24)
+	    );
+
+      arr9: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(72 to 79),
+              DOB   => ramb_data_out(200 to 207),
+              DOPA  => ramb_parity_out(9 to 9),
+              DOPB  => ramb_parity_out(25 to 25),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(72 to 79),
+              DIB   => ramb_data_in(200 to 207),
+              DIPA  => ramb_parity_in(9 to 9),
+              DIPB  => ramb_parity_in(25 to 25),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(9),
+              WEB   => wrt_en_wAH(25)
+	    );
+
+      arrA: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(80 to 87),
+              DOB   => ramb_data_out(208 to 215),
+              DOPA  => ramb_parity_out(10 to 10),
+              DOPB  => ramb_parity_out(26 to 26),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(80 to 87),
+              DIB   => ramb_data_in(208 to 215),
+              DIPA  => ramb_parity_in(10 to 10),
+              DIPB  => ramb_parity_in(26 to 26),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(10),
+              WEB   => wrt_en_wAH(26)
+	    );
+
+      arrB: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(88 to 95),
+              DOB   => ramb_data_out(216 to 223),
+              DOPA  => ramb_parity_out(11 to 11),
+              DOPB  => ramb_parity_out(27 to 27),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(88 to 95),
+              DIB   => ramb_data_in(216 to 223),
+              DIPA  => ramb_parity_in(11 to 11),
+              DIPB  => ramb_parity_in(27 to 27),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(11),
+              WEB   => wrt_en_wAH(27)
+	    );
+
+      arrC: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(96 to 103),
+              DOB   => ramb_data_out(224 to 231),
+              DOPA  => ramb_parity_out(12 to 12),
+              DOPB  => ramb_parity_out(28 to 28),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(96 to 103),
+              DIB   => ramb_data_in(224 to 231),
+              DIPA  => ramb_parity_in(12 to 12),
+              DIPB  => ramb_parity_in(28 to 28),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(12),
+              WEB   => wrt_en_wAH(28)
+	    );
+
+      arrD: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(104 to 111),
+              DOB   => ramb_data_out(232 to 239),
+              DOPA  => ramb_parity_out(13 to 13),
+              DOPB  => ramb_parity_out(29 to 29),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(104 to 111),
+              DIB   => ramb_data_in(232 to 239),
+              DIPA  => ramb_parity_in(13 to 13),
+              DIPB  => ramb_parity_in(29 to 29),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(13),
+              WEB   => wrt_en_wAH(29)
+	    );
+
+      arrE: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(112 to 119),
+              DOB   => ramb_data_out(240 to 247),
+              DOPA  => ramb_parity_out(14 to 14),
+              DOPB  => ramb_parity_out(30 to 30),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(112 to 119),
+              DIB   => ramb_data_in(240 to 247),
+              DIPA  => ramb_parity_in(14 to 14),
+              DIPB  => ramb_parity_in(30 to 30),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(14),
+              WEB   => wrt_en_wAH(30)
+	    );
+
+      arrF: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(120 to 127),
+              DOB   => ramb_data_out(248 to 255),
+              DOPA  => ramb_parity_out(15 to 15),
+              DOPB  => ramb_parity_out(31 to 31),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(120 to 127),
+              DIB   => ramb_data_in(248 to 255),
+              DIPA  => ramb_parity_in(15 to 15),
+              DIPB  => ramb_parity_in(31 to 31),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(15),
+              WEB   => wrt_en_wAH(31)
+	    );
+
+      abst_scan_out <= (others=>'0');
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= (others=>'0');
+      bo_pc_diagloop <= (others=>'0');
+
+      unused <= or_reduce( bw(32 to port_bitwidth-1)
+                       & clkoff_dc_b & ccflush_dc & scan_dis_dc_b & scan_diag_dc & d_mode_dc & act_dis_dc
+                       & bitw_abist & sg_0 & sg_1
+                       & abst_sl_thold_0 & repr_sl_thold_0 
+                       & time_sl_thold_0 & ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc 
+                       & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist 
+                       & addr_abist & r_wb_abist & abst_scan_in & time_scan_in & repr_scan_in
+                       & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc
+                       & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b
+                       & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b
+                       & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                       & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+  end generate a;
+
+
+end tri_512x288_9;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x36_4w_1r1w.vhdl

@@ -0,0 +1,357 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_64x36_4w_1r1w is
+  generic (addressable_ports : positive := 64;  
+           addressbus_width : positive := 6;    
+           port_bitwidth : positive := 36;      
+           ways : positive := 4;                
+           expand_type : integer := 1);         
+  port (
+    gnd                         : inout power_logic;
+    vdd                         : inout power_logic;
+    vcs                         : inout power_logic;
+    nclk                        : in clk_logic;
+    rd_act                      : in std_ulogic;
+    wr_act                      : in std_ulogic;
+    sg_0                        : in std_ulogic;
+    abst_sl_thold_0             : in std_ulogic;
+    ary_nsl_thold_0             : in std_ulogic;
+    time_sl_thold_0             : in std_ulogic;
+    repr_sl_thold_0             : in std_ulogic;
+    clkoff_dc_b                 : in std_ulogic;
+    ccflush_dc                  : in std_ulogic;
+    scan_dis_dc_b               : in std_ulogic;
+    scan_diag_dc                : in std_ulogic;
+    d_mode_dc                   : in std_ulogic;
+    mpw1_dc_b                   : in std_ulogic_vector(0 to 4);
+    mpw2_dc_b                   : in std_ulogic;
+    delay_lclkr_dc              : in std_ulogic_vector(0 to 4);
+    wr_abst_act                 : in std_ulogic;
+    rd0_abst_act                : in std_ulogic;
+    abist_di                    : in std_ulogic_vector(0 to 3);
+    abist_bw_odd                : in std_ulogic;
+    abist_bw_even               : in std_ulogic;
+    abist_wr_adr                : in std_ulogic_vector(0 to 5);
+    abist_rd0_adr               : in std_ulogic_vector(0 to 5);
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_ena_1                 : in std_ulogic;
+    abist_g8t_rd0_comp_ena      : in std_ulogic;
+    abist_raw_dc_b              : in std_ulogic;
+    obs0_abist_cmp              : in std_ulogic_vector(0 to 3);
+    abst_scan_in                : in std_ulogic_vector(0 to 1);
+    time_scan_in                : in std_ulogic;
+    repr_scan_in                : in std_ulogic;
+    abst_scan_out               : out std_ulogic_vector(0 to 1);
+    time_scan_out               : out std_ulogic;
+    repr_scan_out               : out std_ulogic;
+    lcb_bolt_sl_thold_0         : in std_ulogic;
+    pc_bo_enable_2              : in std_ulogic; 
+    pc_bo_reset                 : in std_ulogic; 
+    pc_bo_unload                : in std_ulogic; 
+    pc_bo_repair                : in std_ulogic; 
+    pc_bo_shdata                : in std_ulogic; 
+    pc_bo_select                : in std_ulogic_vector(0 to 1); 
+    bo_pc_failout               : out std_ulogic_vector(0 to 1); 
+    bo_pc_diagloop              : out std_ulogic_vector(0 to 1);
+    tri_lcb_mpw1_dc_b           : in  std_ulogic;
+    tri_lcb_mpw2_dc_b           : in  std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in  std_ulogic;
+    tri_lcb_clkoff_dc_b         : in  std_ulogic;
+    tri_lcb_act_dis_dc          : in  std_ulogic;
+    wr_way                      : in std_ulogic_vector (0 to (ways-1));
+    wr_addr                     : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in                     : in std_ulogic_vector (0 to (port_bitwidth*ways-1));
+    rd_addr                     : in std_ulogic_vector(0 to (addressbus_width-1));
+    data_out                    : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_64x36_4w_1r1w;
+
+architecture tri_64x36_4w_1r1w of tri_64x36_4w_1r1w is
+
+constant wga_base_width : integer := 72;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+
+
+type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal wr_addr_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal rd_addr_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal way_l2             : std_ulogic_vector (0 TO wr_way'right);
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth*ways-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      wr_addr_latch: tri_rlmreg_p
+        generic map (width => wr_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => wr_addr,
+                  dout        => wr_addr_l2 );
+
+      rd_addr_latch: tri_rlmreg_p
+        generic map (width => rd_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => rd_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => rd_addr,
+                  dout        => rd_addr_l2 );
+
+      way_latch: tri_rlmreg_p
+        generic map (width => wr_way'length, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => wr_way,
+                  dout        => way_l2 );
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => wr_act,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(w*port_bitwidth+x)  when (( write_enable_l2 and wr_addr_l2 = tconv(y, addressbus_width) and 
+                                          way_l2(w)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(rd_addr_l2)*port_bitwidth*ways to tconv(rd_addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out <= tidn & tidn;
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= tidn & tidn;
+      bo_pc_diagloop <= tidn & tidn;
+  end generate um;
+  -- synopsys translate_on
+
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+      -- pragma translate_off
+	generic
+	(
+		SIM_COLLISION_CHECK : string := "none"); 
+      -- pragma translate_on
+	port
+	(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal ramb_data_in       : RAMB_DATA_ARRAY(wr_way'range);
+      signal ramb_data_out      : RAMB_DATA_ARRAY(wr_way'range);
+      signal ramb_rd_addr       : std_logic_vector(0 to ramb_base_addr - 1);
+      signal ramb_wr_addr       : std_logic_vector(0 to ramb_base_addr - 1);
+
+      signal tidn               : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      add0: if (addressbus_width < ramb_base_addr) generate
+      begin
+        ramb_rd_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_rd_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( rd_addr );
+
+        ramb_wr_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_wr_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( wr_addr );
+      end generate;
+      add1: if (addressbus_width >= ramb_base_addr) generate
+      begin
+        ramb_rd_addr <= tconv( rd_addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+        ramb_wr_addr <= tconv( wr_addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+      end generate;
+
+      dw: for w in wr_way'range generate begin
+        din: for i in 0 to (ramb_base_width*ramb_width_mult - 1) generate
+        begin
+          R0: if(i <  port_bitwidth) generate begin ramb_data_in(w)(i) <= data_in(w*port_bitwidth+i); end generate;
+          R1: if(i >= port_bitwidth) generate begin ramb_data_in(w)(i) <= '0'; end generate;
+        end generate din;
+      end generate dw;
+
+      aw: for w in wr_way'range generate begin
+        ax: for x in 0 to (ramb_width_mult - 1) generate begin
+          arr: RAMB16_S36_S36
+            -- pragma translate_off
+            generic map(
+                        sim_collision_check => "none")
+            -- pragma translate_on
+            port map(
+		DOA   => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DOB   => open,
+		DOPA  => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DOPB  => open,
+		ADDRA => ramb_rd_addr,
+		ADDRB => ramb_wr_addr,
+		CLKA  => nclk.clk,
+		CLKB  => nclk.clk,
+		DIA   => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DIB   => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DIPA  => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DIPB  => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		ENA   => rd_act,
+		ENB   => wr_act,
+		SSRA  => nclk.sreset,
+		SSRB  => nclk.sreset,
+		WEA   => tidn,
+		WEB   => wr_way(w)
+	  );
+
+        end generate ax;
+
+        data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) );
+
+      end generate aw;
+
+      abst_scan_out <= tidn & tidn;
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= tidn & tidn;
+      bo_pc_diagloop <= tidn & tidn;
+
+      unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0
+                           & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc
+                           & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b
+                           & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di
+                           & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                           & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                           & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in
+                           & repr_scan_in & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                           & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                           & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                           & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+  end generate a;
+
+
+end tri_64x36_4w_1r1w;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x42_4w_1r1w.vhdl

@@ -0,0 +1,381 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_64x42_4w_1r1w is
+generic(
+   expand_type                         : integer :=  1);
+port (
+   vdd                                 : INOUT power_logic; 
+   vcs                                 : INOUT power_logic; 
+   gnd                                 : INOUT power_logic; 
+
+   nclk                                : in clk_logic;
+   sg_0                                : in  std_ulogic;
+   abst_sl_thold_0                     : in  std_ulogic;
+   ary_nsl_thold_0                     : in  std_ulogic;
+   time_sl_thold_0                     : in  std_ulogic;
+   repr_sl_thold_0                     : in  std_ulogic;
+
+   rd0_act                             : in std_ulogic;
+   rd0_adr                             : in std_ulogic_vector(0 to 5);  
+   do0                                 : out std_ulogic_vector(0 to 167);
+   
+   wr_way                              : in std_ulogic_vector (0 to 3);
+   wr_act            		       : in std_ulogic;
+   wr_adr            		       : in std_ulogic_vector(0 to 5);    		
+   di                		       : in std_ulogic_vector(0 to 167);
+     
+   abst_scan_in                        : in  std_ulogic;
+   abst_scan_out                       : out std_ulogic;
+   time_scan_in                        : in  std_ulogic;
+   time_scan_out                       : out std_ulogic;
+   repr_scan_in                        : in  std_ulogic;
+   repr_scan_out                       : out std_ulogic;
+   
+   scan_dis_dc_b                       : in  std_ulogic;
+   scan_diag_dc                        : in  std_ulogic;
+   ccflush_dc                          : in  std_ulogic;
+   ary0_clkoff_dc_b                    : in  std_ulogic;
+   ary0_d_mode_dc                      : in  std_ulogic;
+   ary0_mpw1_dc_b                      : in  std_ulogic_vector(0 to 4);
+   ary0_mpw2_dc_b                      : in  std_ulogic;
+   ary0_delay_lclkr_dc                 : in  std_ulogic_vector(0 to 4);
+   ary1_clkoff_dc_b                    : in  std_ulogic;
+   ary1_d_mode_dc                      : in  std_ulogic;
+   ary1_mpw1_dc_b                      : in  std_ulogic_vector(0 to 4);
+   ary1_mpw2_dc_b                      : in  std_ulogic;
+   ary1_delay_lclkr_dc                 : in  std_ulogic_vector(0 to 4);
+
+   lcb_bolt_sl_thold_0                 : in  std_ulogic;
+   pc_bo_enable_2                      : in  std_ulogic; 
+   pc_bo_reset                         : in  std_ulogic; 
+   pc_bo_unload                        : in  std_ulogic; 
+   pc_bo_repair                        : in  std_ulogic; 
+   pc_bo_shdata                        : in  std_ulogic; 
+   pc_bo_select                        : in  std_ulogic_vector(0 to 1); 
+   bo_pc_failout                       : out std_ulogic_vector(0 to 1); 
+   bo_pc_diagloop                      : out std_ulogic_vector(0 to 1);
+   tri_lcb_mpw1_dc_b                   : in  std_ulogic;
+   tri_lcb_mpw2_dc_b                   : in  std_ulogic;
+   tri_lcb_delay_lclkr_dc              : in  std_ulogic;
+   tri_lcb_clkoff_dc_b                 : in  std_ulogic;
+   tri_lcb_act_dis_dc                  : in  std_ulogic;
+
+   abist_di                            : in  std_ulogic_vector(0 to 3);
+   abist_bw_odd                        : in  std_ulogic;
+   abist_bw_even                       : in  std_ulogic;
+   abist_wr_adr                        : in  std_ulogic_vector(0 to 5);
+   wr_abst_act                         : in  std_ulogic;
+   abist_rd0_adr                       : in  std_ulogic_vector(0 to 5);
+   rd0_abst_act                        : in  std_ulogic;
+   tc_lbist_ary_wrt_thru_dc            : in  std_ulogic;
+   abist_ena_1                         : in  std_ulogic;
+   abist_g8t_rd0_comp_ena              : in  std_ulogic;
+   abist_raw_dc_b                      : in  std_ulogic;
+   obs0_abist_cmp                      : in  std_ulogic_vector(0 to 3)
+   );
+
+-- synopsys translate_off
+-- synopsys translate_on
+
+
+end entity tri_64x42_4w_1r1w;
+architecture tri_64x42_4w_1r1w of tri_64x42_4w_1r1w is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal clk,             clk2x             : std_ulogic;
+signal addra,           addrb             : std_ulogic_vector(0 to 8);
+signal wea0, wea1, wea2, wea3             : std_ulogic;
+signal web0, web1, web2, web3             : std_ulogic;
+signal bdo0, bdo1, bdo2, bdo3             : std_logic_vector(0 to 71);
+signal bdi0, bdi1, bdi2, bdi3             : std_ulogic_vector(0 to 71);
+signal sreset                             : std_ulogic;
+signal tidn                               : std_ulogic_vector(36 to 65);
+signal reset_q                            : std_ulogic;
+signal gate_fq,         gate_d            : std_ulogic;
+signal bdo_d,           bdo_fq            : std_ulogic_vector(0 to 167);
+
+signal toggle_d     : std_ulogic;
+signal toggle_q     : std_ulogic;
+signal toggle2x_d   : std_ulogic;
+signal toggle2x_q   : std_ulogic;
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+tidn  <= (others=>'0');
+clk   <= nclk.clk;
+clk2x <= nclk.clk2x;
+sreset<= nclk.sreset;
+
+rlatch: process (clk) begin
+    if(rising_edge(clk)) then
+      reset_q              <= sreset after 10 ps;
+    end if;
+end process;
+
+
+tlatch: process (nclk.clk,reset_q)
+begin
+   if(rising_edge(nclk.clk)) then
+      if (reset_q = '1') then
+         toggle_q  <= '1';
+      else
+         toggle_q  <= toggle_d;
+      end if;
+    end if;
+end process;
+
+flatch: process (nclk.clk2x)
+begin
+   if(rising_edge(nclk.clk2x)) then
+      toggle2x_q <= toggle2x_d;
+      gate_fq  <= gate_d;
+      bdo_fq   <= bdo_d;
+   end if;
+end process;
+
+toggle_d   <= not toggle_q;
+toggle2x_d <= toggle_q;
+
+gate_d <= not(toggle_q xor toggle2x_q);
+
+
+
+
+
+
+
+   bdi0        <= di(0   to  35) & tidn(36 to 65) & di(36  to  41);
+   bdi1        <= di(42  to  77) & tidn(36 to 65) & di(78  to  83);
+   bdi2        <= di(84  to 119) & tidn(36 to 65) & di(120 to 125);
+   bdi3        <= di(126 to 161) & tidn(36 to 65) & di(162 to 167);
+
+bdo_d(0   to  41) <= std_ulogic_vector(bdo0(0 to 35) & bdo0(66 to 71));
+bdo_d(42  to  83) <= std_ulogic_vector(bdo1(0 to 35) & bdo1(66 to 71));
+bdo_d(84  to 125) <= std_ulogic_vector(bdo2(0 to 35) & bdo2(66 to 71));
+bdo_d(126 to 167) <= std_ulogic_vector(bdo3(0 to 35) & bdo3(66 to 71));
+
+do0         <= bdo_fq;
+
+wea0        <= (wr_act and gate_fq and wr_way(0)) after 10 ps;
+web0        <= (wr_act and gate_fq and wr_way(0)) after 10 ps;
+wea1        <= (wr_act and gate_fq and wr_way(1)) after 10 ps;
+web1        <= (wr_act and gate_fq and wr_way(1)) after 10 ps;
+wea2        <= (wr_act and gate_fq and wr_way(2)) after 10 ps;
+web2        <= (wr_act and gate_fq and wr_way(2)) after 10 ps;
+wea3        <= (wr_act and gate_fq and wr_way(3)) after 10 ps;
+web3        <= (wr_act and gate_fq and wr_way(3)) after 10 ps;
+
+with gate_fq select
+   addra    <= ("00" & wr_adr  & '0') after 10 ps  when '1',
+               ("00" & rd0_adr & '0') after 10 ps when others;
+
+with gate_fq select
+   addrb    <= ("00" & wr_adr  & '1') after 10 ps when '1',
+               ("00" & rd0_adr & '1') after 10 ps when others;
+
+bram0a : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi0(00 to 31)),
+	               dipa  => std_logic_vector(bdi0(32 to 35)),
+	               dib   => std_logic_vector(bdi0(36 to 67)),
+	               dipb  => std_logic_vector(bdi0(68 to 71)),
+                  doa   => bdo0(00 to 31),
+                  dopa  => bdo0(32 to 35),
+                  dob   => bdo0(36 to 67),
+                  dopb  => bdo0(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea0,
+	               web   => web0
+	               );
+
+bram0b : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi1(00 to 31)),
+	               dipa  => std_logic_vector(bdi1(32 to 35)),
+	               dib   => std_logic_vector(bdi1(36 to 67)),
+	               dipb  => std_logic_vector(bdi1(68 to 71)),
+                  doa   => bdo1(00 to 31),
+                  dopa  => bdo1(32 to 35),
+                  dob   => bdo1(36 to 67),
+                  dopb  => bdo1(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea1,
+	               web   => web1
+	               );
+
+bram0c : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi2(00 to 31)),
+	               dipa  => std_logic_vector(bdi2(32 to 35)),
+	               dib   => std_logic_vector(bdi2(36 to 67)),
+	               dipb  => std_logic_vector(bdi2(68 to 71)),
+                  doa   => bdo2(00 to 31),
+                  dopa  => bdo2(32 to 35),
+                  dob   => bdo2(36 to 67),
+                  dopb  => bdo2(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea2,
+	               web   => web2
+	               );
+
+
+bram0d : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi3(00 to 31)),
+	               dipa  => std_logic_vector(bdi3(32 to 35)),
+	               dib   => std_logic_vector(bdi3(36 to 67)),
+	               dipb  => std_logic_vector(bdi3(68 to 71)),
+                  doa   => bdo3(00 to 31),
+                  dopa  => bdo3(32 to 35),
+                  dob   => bdo3(36 to 67),
+                  dopb  => bdo3(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea3,
+	               web   => web3
+	               );
+
+
+abst_scan_out  <= abst_scan_in;
+time_scan_out  <= time_scan_in;
+repr_scan_out  <= repr_scan_in;
+
+bo_pc_failout <= "00";
+bo_pc_diagloop <= "00";
+
+unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0
+                     & ary0_clkoff_dc_b & ary0_d_mode_dc & ary0_mpw1_dc_b & ary0_mpw2_dc_b
+                     & ary0_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc
+                     & ary1_clkoff_dc_b & ary1_d_mode_dc & ary1_mpw1_dc_b & ary1_mpw2_dc_b
+                     & ary1_delay_lclkr_dc & abist_di
+                     & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                     & wr_abst_act & rd0_abst_act
+                     & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                     & abist_raw_dc_b & obs0_abist_cmp & rd0_act
+                     & std_ulogic_vector( bdo0(36 to 65) ) & std_ulogic_vector( bdo1(36 to 65) )
+                     & std_ulogic_vector( bdo2(36 to 65) ) & std_ulogic_vector( bdo3(36 to 65) )
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate;
+
+end architecture tri_64x42_4w_1r1w;
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x72_1r1w.vhdl

@@ -0,0 +1,285 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_64x72_1r1w is
+generic(
+   expand_type                         : integer :=  1;
+   regsize                             : integer := 64);
+port (
+   vdd                                 : INOUT power_logic; 
+   vcs                                 : INOUT power_logic; 
+   gnd                                 : INOUT power_logic; 
+
+   nclk                                : in clk_logic;
+   sg_0                                : in  std_ulogic;
+   abst_sl_thold_0                     : in  std_ulogic;
+   ary_nsl_thold_0                     : in  std_ulogic;
+   time_sl_thold_0                     : in  std_ulogic;
+   repr_sl_thold_0                     : in  std_ulogic;
+
+   rd0_act                             : in std_ulogic;
+   rd0_adr                             : in std_ulogic_vector(0 to 5);  
+   do0                                 : out std_ulogic_vector(64-regsize to 72-(64/regsize));
+
+   wr_act                              : in std_ulogic;
+   wr_adr                              : in std_ulogic_vector(0 to 5);
+   di                                  : in std_ulogic_vector(64-regsize to 72-(64/regsize));
+
+   abst_scan_in                        : in  std_ulogic;
+   abst_scan_out                       : out std_ulogic;
+   time_scan_in                        : in  std_ulogic;
+   time_scan_out                       : out std_ulogic;
+   repr_scan_in                        : in  std_ulogic;
+   repr_scan_out                       : out std_ulogic;
+   
+   scan_dis_dc_b                       : in  std_ulogic;
+   scan_diag_dc                        : in  std_ulogic;
+   ccflush_dc                          : in  std_ulogic;
+   clkoff_dc_b                         : in  std_ulogic;
+   d_mode_dc                           : in  std_ulogic;
+   mpw1_dc_b                           : in  std_ulogic_vector(0 to 4);
+   mpw2_dc_b                           : in  std_ulogic;
+   delay_lclkr_dc                      : in  std_ulogic_vector(0 to 4);
+
+   lcb_bolt_sl_thold_0                 : in  std_ulogic;
+   pc_bo_enable_2                      : in  std_ulogic; 
+   pc_bo_reset                         : in  std_ulogic; 
+   pc_bo_unload                        : in  std_ulogic; 
+   pc_bo_repair                        : in  std_ulogic; 
+   pc_bo_shdata                        : in  std_ulogic; 
+   pc_bo_select                        : in  std_ulogic; 
+   bo_pc_failout                       : out std_ulogic; 
+   bo_pc_diagloop                      : out std_ulogic;
+   tri_lcb_mpw1_dc_b                   : in  std_ulogic;
+   tri_lcb_mpw2_dc_b                   : in  std_ulogic;
+   tri_lcb_delay_lclkr_dc              : in  std_ulogic;
+   tri_lcb_clkoff_dc_b                 : in  std_ulogic;
+   tri_lcb_act_dis_dc                  : in  std_ulogic;
+
+   abist_di                            : in  std_ulogic_vector(0 to 3);
+   abist_bw_odd                        : in  std_ulogic;
+   abist_bw_even                       : in  std_ulogic;
+   abist_wr_adr                        : in  std_ulogic_vector(0 to 5);
+   wr_abst_act                         : in  std_ulogic;
+   abist_rd0_adr                       : in  std_ulogic_vector(0 to 5);
+   rd0_abst_act                        : in  std_ulogic;
+   tc_lbist_ary_wrt_thru_dc            : in  std_ulogic;
+   abist_ena_1                         : in  std_ulogic;
+   abist_g8t_rd0_comp_ena              : in  std_ulogic;
+   abist_raw_dc_b                      : in  std_ulogic;
+   obs0_abist_cmp                      : in  std_ulogic_vector(0 to 3)
+   );
+
+-- synopsys translate_off
+-- synopsys translate_on
+
+
+end entity tri_64x72_1r1w;
+architecture tri_64x72_1r1w of tri_64x72_1r1w is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal clk,             clk2x             : std_ulogic;
+signal addra,           addrb             : std_ulogic_vector(0 to 8);
+signal wea,             web               : std_ulogic;
+signal bdo                                : std_logic_vector(0 to 71);
+signal bdi                                : std_ulogic_vector(0 to 71);
+signal sreset                             : std_ulogic;
+signal tidn                               : std_ulogic_vector(0 to 71);
+signal reset_q                            : std_ulogic;
+signal gate_fq,         gate_d            : std_ulogic;
+signal bdo_d,           bdo_fq            : std_ulogic_vector(64-regsize to 72-(64/regsize));
+
+signal toggle_d     : std_ulogic;
+signal toggle_q     : std_ulogic;
+signal toggle2x_d   : std_ulogic;
+signal toggle2x_q   : std_ulogic;
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+tidn  <= (others=>'0');
+clk   <= nclk.clk;
+clk2x <= nclk.clk2x;
+sreset<= nclk.sreset;
+
+rlatch: process (clk) begin
+    if(rising_edge(clk)) then
+      reset_q              <= sreset after 10 ps;
+    end if;
+end process;
+
+
+tlatch: process (nclk.clk,reset_q)
+begin
+   if(rising_edge(nclk.clk)) then
+      if (reset_q = '1') then
+         toggle_q  <= '1';
+      else
+         toggle_q  <= toggle_d;
+      end if;
+    end if;
+end process;
+
+flatch: process (nclk.clk2x)
+begin
+   if(rising_edge(nclk.clk2x)) then
+      toggle2x_q <= toggle2x_d;
+      gate_fq  <= gate_d;
+      bdo_fq   <= bdo_d;
+   end if;
+end process;
+
+toggle_d   <= not toggle_q;
+toggle2x_d <= toggle_q;
+
+gate_d <= not(toggle_q xor toggle2x_q);
+
+
+
+
+
+
+in32 : if regsize = 32 generate
+   bdi         <= tidn(0 to 31) & di(32 to 63) & di(64 to 70) & tidn(71);
+end generate;
+in64 : if regsize = 64 generate
+   bdi         <= di(0 to 71);
+end generate;
+
+bdo_d       <= std_ulogic_vector(bdo(64-regsize to 72-(64/regsize)));
+do0         <= bdo_fq;
+
+wea         <= (wr_act and gate_fq) after 10 ps;
+web         <= (wr_act and gate_fq) after 10 ps;
+
+with gate_fq select
+   addra    <= ("00" & wr_adr  & '0') after 10 ps  when '1',
+               ("00" & rd0_adr & '0') after 10 ps when others;
+
+with gate_fq select
+   addrb    <= ("00" & wr_adr  & '1') after 10 ps when '1',
+               ("00" & rd0_adr & '1') after 10 ps when others;
+
+bram0a : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi(00 to 31)),
+	               dib   => std_logic_vector(bdi(32 to 63)),
+	               dipa  => std_logic_vector(bdi(64 to 67)),
+	               dipb  => std_logic_vector(bdi(68 to 71)),
+                  doa   => bdo(00 to 31),
+                  dob   => bdo(32 to 63),
+                  dopa  => bdo(64 to 67),
+                  dopb  => bdo(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea,
+	               web   => web
+	               );
+                  
+
+abst_scan_out  <= abst_scan_in;
+time_scan_out  <= time_scan_in;
+repr_scan_out  <= repr_scan_in;
+
+bo_pc_failout <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0
+                     & scan_dis_dc_b & scan_diag_dc & ccflush_dc
+                     & clkoff_dc_b & d_mode_dc & mpw1_dc_b & mpw2_dc_b
+                     & delay_lclkr_dc & abist_di
+                     & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                     & wr_abst_act & rd0_abst_act
+                     & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                     & abist_raw_dc_b & obs0_abist_cmp & rd0_act & tidn
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+
+end generate;
+
+end architecture tri_64x72_1r1w;
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats.vhdl

@@ -0,0 +1,122 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;    use ieee.std_logic_1164.all;
+                 use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri;     use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_aoi22_nlats is
+
+  generic (
+            offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ; 
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "NLL0001_X2_A12TH" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        LCLK     : in    clk_logic; 
+        D1CLK    : in    std_ulogic; 
+        D2CLK    : in    std_ulogic; 
+        SCANIN   : in    std_ulogic_vector(offset to offset+width-1);
+        SCANOUT  : out   std_ulogic_vector(offset to offset+width-1);
+        A1       : in    std_ulogic_vector(offset to offset+width-1); 
+        A2       : in    std_ulogic_vector(offset to offset+width-1); 
+        B1       : in    std_ulogic_vector(offset to offset+width-1); 
+        B2       : in    std_ulogic_vector(offset to offset+width-1); 
+        QB       : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_aoi22_nlats;
+
+architecture tri_aoi22_nlats of tri_aoi22_nlats is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal din : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width-1);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= LCLK.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    din   <= (A1 and A2) or (B1 and B2) ;       
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact   <= (0 to width-1 =>     D1CLK);
+    vact_b <= (0 to width-1 => not D1CLK);
+
+    vthold_b <= (0 to width-1 => D2CLK);
+    vthold   <= (0 to width-1 => not D2CLK);
+
+    l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(LCLK.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    QB <= not int_dout;
+    SCANOUT <= zeros;
+
+    unused <= SCANIN;
+  end generate a;
+
+end tri_aoi22_nlats;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats_wlcb.vhdl

@@ -0,0 +1,133 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_aoi22_nlats_wlcb is
+
+  generic (
+    width       : integer := 4;
+    offset      : integer range 0 to 65535 := 0 ; 
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 ; 
+    synthclonedlatch   : string                    := "" ;
+    btr                : string                    := "NLL0001_X2_A12TH" );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    sg      : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    scin    : in  std_ulogic_vector(offset to offset+width-1);  
+    scout   : out std_ulogic_vector(offset to offset+width-1);
+    A1       : in    std_ulogic_vector(offset to offset+width-1); 
+    A2       : in    std_ulogic_vector(offset to offset+width-1); 
+    B1       : in    std_ulogic_vector(offset to offset+width-1); 
+    B2       : in    std_ulogic_vector(offset to offset+width-1); 
+    QB       : out   std_ulogic_vector(offset to offset+width-1));
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_aoi22_nlats_wlcb;
+
+architecture tri_aoi22_nlats_wlcb of tri_aoi22_nlats_wlcb is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din, din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+
+    din   <= (A1 and A2) or (B1 and B2) ;       
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v);
+
+    vact <= (0 to width-1 => (act or forcee));
+    vact_b <= (0 to width-1 => not (act or forcee));
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+
+    QB <= not int_dout;
+
+    scout <= zeros;
+
+    unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b;
+    unused(1 to width) <= scin;
+  end generate a;
+
+end tri_aoi22_nlats_wlcb;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_bht.vhdl

@@ -0,0 +1,501 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+use ibm.std_ulogic_unsigned.all;
+
+library support;
+use support.power_logic_pkg.all;
+
+library tri;
+use tri.tri_latches_pkg.all;
+
+
+entity tri_bht is
+generic(expand_type : integer := 1 ); 
+port(
+     gnd                        : inout power_logic;
+     vdd                        : inout power_logic;
+     vcs                        : inout power_logic;
+
+     nclk                       : in  clk_logic; 
+     pc_iu_func_sl_thold_2      : in  std_ulogic;
+     pc_iu_sg_2                 : in  std_ulogic;
+     pc_iu_time_sl_thold_2      : in  std_ulogic;
+     pc_iu_abst_sl_thold_2      : in  std_ulogic;
+     pc_iu_ary_nsl_thold_2      : in  std_ulogic;
+     pc_iu_repr_sl_thold_2      : in  std_ulogic;
+     pc_iu_bolt_sl_thold_2      : in  std_ulogic;
+     tc_ac_ccflush_dc           : in  std_ulogic;
+     tc_ac_scan_dis_dc_b        : in  std_ulogic;
+     clkoff_b                   : in  std_ulogic;
+     scan_diag_dc               : in  std_ulogic;
+     act_dis                    : in  std_ulogic;
+     d_mode                     : in  std_ulogic;
+     delay_lclkr                : in  std_ulogic;
+     mpw1_b                     : in  std_ulogic;
+     mpw2_b                     : in  std_ulogic;
+     g8t_clkoff_b               : in  std_ulogic;
+     g8t_d_mode                 : in  std_ulogic;
+     g8t_delay_lclkr            : in  std_ulogic_vector(0 to 4);
+     g8t_mpw1_b                 : in  std_ulogic_vector(0 to 4);
+     g8t_mpw2_b                 : in  std_ulogic;
+     func_scan_in               : in  std_ulogic;
+     time_scan_in               : in  std_ulogic;
+     abst_scan_in               : in  std_ulogic;
+     repr_scan_in               : in  std_ulogic;
+     func_scan_out              : out std_ulogic;
+     time_scan_out              : out std_ulogic;
+     abst_scan_out              : out std_ulogic;
+     repr_scan_out              : out std_ulogic;
+
+     pc_iu_abist_di_0           : in  std_ulogic_vector(0 to 3);
+     pc_iu_abist_g8t_bw_1       : in  std_ulogic;
+     pc_iu_abist_g8t_bw_0       : in  std_ulogic;
+     pc_iu_abist_waddr_0        : in  std_ulogic_vector(3 to 9);
+     pc_iu_abist_g8t_wenb       : in  std_ulogic;
+     pc_iu_abist_raddr_0        : in  std_ulogic_vector(3 to 9);
+     pc_iu_abist_g8t1p_renb_0   : in  std_ulogic;
+     an_ac_lbist_ary_wrt_thru_dc: in  std_ulogic;
+     pc_iu_abist_ena_dc         : in  std_ulogic;
+     pc_iu_abist_wl128_comp_ena : in  std_ulogic;
+     pc_iu_abist_raw_dc_b       : in  std_ulogic;
+     pc_iu_abist_g8t_dcomp      : in  std_ulogic_vector(0 to 3);
+
+     pc_iu_bo_enable_2          : in  std_ulogic; 
+     pc_iu_bo_reset             : in  std_ulogic; 
+     pc_iu_bo_unload            : in  std_ulogic; 
+     pc_iu_bo_repair            : in  std_ulogic; 
+     pc_iu_bo_shdata            : in  std_ulogic; 
+     pc_iu_bo_select            : in  std_ulogic; 
+     iu_pc_bo_fail              : out std_ulogic; 
+     iu_pc_bo_diagout           : out std_ulogic;
+
+     r_act                      : in  std_ulogic;
+     w_act                      : in  std_ulogic_vector(0 to 3);
+     r_addr                     : in  std_ulogic_vector(0 to 7);
+     w_addr                     : in  std_ulogic_vector(0 to 7);
+     data_in                    : in  std_ulogic_vector(0 to 1);
+     data_out0                  : out std_ulogic_vector(0 to 1);
+     data_out1                  : out std_ulogic_vector(0 to 1);
+     data_out2                  : out std_ulogic_vector(0 to 1);
+     data_out3                  : out std_ulogic_vector(0 to 1)
+
+);
+
+-- pragma translate_off
+
+
+-- pragma translate_on
+
+end tri_bht;
+architecture tri_bht of tri_bht is
+
+
+constant data_in_offset                 : natural := 0;
+constant w_act_offset                   : natural := data_in_offset     + 2;
+constant r_act_offset                   : natural := w_act_offset       + 4;
+constant w_addr_offset                  : natural := r_act_offset       + 1;
+constant r_addr_offset                  : natural := w_addr_offset      + 8;
+constant data_out_offset                : natural := r_addr_offset      + 8;
+constant array_offset                   : natural := data_out_offset    + 8;
+constant scan_right                     : natural := array_offset       + 1 - 1;
+
+constant INIT_MASK                      : std_ulogic_vector(0 to 1) := "10";
+
+
+signal pc_iu_func_sl_thold_1    : std_ulogic;
+signal pc_iu_func_sl_thold_0    : std_ulogic;
+signal pc_iu_func_sl_thold_0_b  : std_ulogic;
+signal pc_iu_time_sl_thold_1    : std_ulogic;
+signal pc_iu_time_sl_thold_0    : std_ulogic;
+signal pc_iu_ary_nsl_thold_1    : std_ulogic;
+signal pc_iu_ary_nsl_thold_0    : std_ulogic;
+signal pc_iu_abst_sl_thold_1    : std_ulogic;
+signal pc_iu_abst_sl_thold_0    : std_ulogic;
+signal pc_iu_repr_sl_thold_1    : std_ulogic;
+signal pc_iu_repr_sl_thold_0    : std_ulogic;
+signal pc_iu_bolt_sl_thold_1    : std_ulogic;
+signal pc_iu_bolt_sl_thold_0    : std_ulogic;
+signal pc_iu_sg_1               : std_ulogic;
+signal pc_iu_sg_0               : std_ulogic;
+signal forcee                    : std_ulogic;
+
+signal siv              : std_ulogic_vector(0 to scan_right);
+signal sov              : std_ulogic_vector(0 to scan_right);
+
+signal tiup             : std_ulogic;
+
+signal data_out_d       : std_ulogic_vector(0 to 7);
+signal data_out_q       : std_ulogic_vector(0 to 7);
+
+signal ary_w_en         : std_ulogic;
+signal ary_w_addr       : std_ulogic_vector(0 to 6);
+signal ary_w_sel        : std_ulogic_vector(0 to 15);
+signal ary_w_data       : std_ulogic_vector(0 to 15);
+
+signal ary_r_en         : std_ulogic;
+signal ary_r_addr       : std_ulogic_vector(0 to 6);
+signal ary_r_data       : std_ulogic_vector(0 to 15);
+
+signal data_out         : std_ulogic_vector(0 to 7);
+signal write_thru       : std_ulogic_vector(0 to 3);
+
+signal data_in_d        : std_ulogic_vector(0 to 1);
+signal data_in_q        : std_ulogic_vector(0 to 1);
+signal w_act_d          : std_ulogic_vector(0 to 3);
+signal w_act_q          : std_ulogic_vector(0 to 3);
+signal r_act_d          : std_ulogic;
+signal r_act_q          : std_ulogic;
+signal w_addr_d         : std_ulogic_vector(0 to 7);
+signal w_addr_q         : std_ulogic_vector(0 to 7);
+signal r_addr_d         : std_ulogic_vector(0 to 7);
+signal r_addr_q         : std_ulogic_vector(0 to 7);
+
+
+begin
+
+
+tiup    <= '1';
+
+
+data_out0(0 to 1)       <= data_out_q(0 to 1);
+data_out1(0 to 1)       <= data_out_q(2 to 3);
+data_out2(0 to 1)       <= data_out_q(4 to 5);
+data_out3(0 to 1)       <= data_out_q(6 to 7);
+
+
+ary_w_en                <= or_reduce(w_act(0 to 3)) and not ((w_addr(1 to 7) = r_addr(1 to 7)) and r_act = '1');
+
+ary_w_addr(0 to 6)      <= w_addr(1 to 7);
+
+ary_w_sel(0)            <= w_act(0) and w_addr(0) = '0';
+ary_w_sel(1)            <= w_act(0) and w_addr(0) = '0';
+ary_w_sel(2)            <= w_act(1) and w_addr(0) = '0';
+ary_w_sel(3)            <= w_act(1) and w_addr(0) = '0';
+ary_w_sel(4)            <= w_act(2) and w_addr(0) = '0';
+ary_w_sel(5)            <= w_act(2) and w_addr(0) = '0';
+ary_w_sel(6)            <= w_act(3) and w_addr(0) = '0';
+ary_w_sel(7)            <= w_act(3) and w_addr(0) = '0';
+ary_w_sel(8)            <= w_act(0) and w_addr(0) = '1';
+ary_w_sel(9)            <= w_act(0) and w_addr(0) = '1';
+ary_w_sel(10)           <= w_act(1) and w_addr(0) = '1';
+ary_w_sel(11)           <= w_act(1) and w_addr(0) = '1';
+ary_w_sel(12)           <= w_act(2) and w_addr(0) = '1';
+ary_w_sel(13)           <= w_act(2) and w_addr(0) = '1';
+ary_w_sel(14)           <= w_act(3) and w_addr(0) = '1';
+ary_w_sel(15)           <= w_act(3) and w_addr(0) = '1';
+
+ary_w_data(0 to 15)     <= (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) ;
+
+ary_r_en                <= r_act;
+
+ary_r_addr(0 to 6)      <= r_addr(1 to 7);
+
+data_out(0 to 7)        <= gate(ary_r_data(0 to 7)  xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '0') or
+                           gate(ary_r_data(8 to 15) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '1') ;
+
+
+data_in_d(0 to 1)       <= data_in(0 to 1);
+w_act_d(0 to 3)         <= w_act(0 to 3);
+r_act_d                 <= r_act;
+w_addr_d(0 to 7)        <= w_addr(0 to 7);
+r_addr_d(0 to 7)        <= r_addr(0 to 7);
+
+write_thru(0 to 3)      <= w_act_q(0 to 3) when (w_addr_q(0 to 7) = r_addr_q(0 to 7)) and r_act_q = '1' else "0000";
+
+data_out_d(0 to 1)      <= data_in_q(0 to 1) when write_thru(0) = '1' else
+                           data_out(0 to 1);
+data_out_d(2 to 3)      <= data_in_q(0 to 1) when write_thru(1) = '1' else
+                           data_out(2 to 3);
+data_out_d(4 to 5)      <= data_in_q(0 to 1) when write_thru(2) = '1' else
+                           data_out(4 to 5);
+data_out_d(6 to 7)      <= data_in_q(0 to 1) when write_thru(3) = '1' else
+                           data_out(6 to 7);
+
+
+bht0: entity tri.tri_128x16_1r1w_1
+  generic map ( expand_type => expand_type )
+  port map(
+           gnd                          => gnd,
+           vdd                          => vdd,
+           vcs                          => vcs,
+           nclk                         => nclk,
+
+           rd_act                       => ary_r_en,              
+           wr_act                       => ary_w_en,		    
+
+           lcb_d_mode_dc                => g8t_d_mode,           
+           lcb_clkoff_dc_b              => g8t_clkoff_b,      
+           lcb_mpw1_dc_b                => g8t_mpw1_b, 
+           lcb_mpw2_dc_b                => g8t_mpw2_b,                  
+           lcb_delay_lclkr_dc           => g8t_delay_lclkr,
+           ccflush_dc                   => tc_ac_ccflush_dc,
+           scan_dis_dc_b                => tc_ac_scan_dis_dc_b,
+           scan_diag_dc                 => scan_diag_dc,
+           func_scan_in                 => siv(array_offset),
+           func_scan_out                => sov(array_offset),
+
+           lcb_sg_0                     => pc_iu_sg_0,                      
+           lcb_sl_thold_0_b             => pc_iu_func_sl_thold_0_b,     
+           lcb_time_sl_thold_0          => pc_iu_time_sl_thold_0,
+           lcb_abst_sl_thold_0          => pc_iu_abst_sl_thold_0,
+           lcb_ary_nsl_thold_0          => pc_iu_ary_nsl_thold_0,
+           lcb_repr_sl_thold_0          => pc_iu_repr_sl_thold_0,
+           time_scan_in                 => time_scan_in,
+           time_scan_out                => time_scan_out,
+           abst_scan_in                 => abst_scan_in,
+           abst_scan_out                => abst_scan_out,
+           repr_scan_in                 => repr_scan_in,
+           repr_scan_out                => repr_scan_out,
+
+           abist_di                     => pc_iu_abist_di_0,
+           abist_bw_odd                 => pc_iu_abist_g8t_bw_1,
+           abist_bw_even                => pc_iu_abist_g8t_bw_0,
+           abist_wr_adr                 => pc_iu_abist_waddr_0,
+           wr_abst_act                  => pc_iu_abist_g8t_wenb,
+           abist_rd0_adr                => pc_iu_abist_raddr_0,
+           rd0_abst_act                 => pc_iu_abist_g8t1p_renb_0,
+           tc_lbist_ary_wrt_thru_dc     => an_ac_lbist_ary_wrt_thru_dc,
+           abist_ena_1                  => pc_iu_abist_ena_dc,        
+           abist_g8t_rd0_comp_ena       => pc_iu_abist_wl128_comp_ena,
+           abist_raw_dc_b               => pc_iu_abist_raw_dc_b,
+           obs0_abist_cmp               => pc_iu_abist_g8t_dcomp,
+
+           lcb_bolt_sl_thold_0          => pc_iu_bolt_sl_thold_0,
+           pc_bo_enable_2               => pc_iu_bo_enable_2,
+           pc_bo_reset                  => pc_iu_bo_reset,
+           pc_bo_unload                 => pc_iu_bo_unload,
+           pc_bo_repair                 => pc_iu_bo_repair,
+           pc_bo_shdata                 => pc_iu_bo_shdata,
+           pc_bo_select                 => pc_iu_bo_select,
+           bo_pc_failout                => iu_pc_bo_fail,
+           bo_pc_diagloop               => iu_pc_bo_diagout,
+
+           tri_lcb_mpw1_dc_b            => mpw1_b,
+           tri_lcb_mpw2_dc_b            => mpw2_b,
+           tri_lcb_delay_lclkr_dc       => delay_lclkr,
+           tri_lcb_clkoff_dc_b          => clkoff_b,
+           tri_lcb_act_dis_dc           => act_dis,
+
+           bw                           => ary_w_sel,     
+           wr_adr                       => ary_w_addr,     
+           rd_adr                       => ary_r_addr,     
+           di                           => ary_w_data,     
+           do                           => ary_r_data
+);
+
+
+
+
+data_in_reg: tri_rlmreg_p
+generic map (width => data_in_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(data_in_offset to data_in_offset + data_in_q'length-1),
+          scout       => sov(data_in_offset to data_in_offset + data_in_q'length-1),
+          din         => data_in_d,
+          dout        => data_in_q);
+
+w_act_reg: tri_rlmreg_p
+generic map (width => w_act_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(w_act_offset to w_act_offset + w_act_q'length-1),
+          scout       => sov(w_act_offset to w_act_offset + w_act_q'length-1),
+          din         => w_act_d,
+          dout        => w_act_q);
+
+r_act_reg: tri_rlmlatch_p
+generic map (init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(r_act_offset),
+          scout       => sov(r_act_offset),
+          din         => r_act_d,
+          dout        => r_act_q);
+
+w_addr_reg: tri_rlmreg_p
+generic map (width => w_addr_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(w_addr_offset to w_addr_offset + w_addr_q'length-1),
+          scout       => sov(w_addr_offset to w_addr_offset + w_addr_q'length-1),
+          din         => w_addr_d,
+          dout        => w_addr_q);
+
+r_addr_reg: tri_rlmreg_p
+generic map (width => r_addr_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(r_addr_offset to r_addr_offset + r_addr_q'length-1),
+          scout       => sov(r_addr_offset to r_addr_offset + r_addr_q'length-1),
+          din         => r_addr_d,
+          dout        => r_addr_q);
+
+
+data_out_reg: tri_rlmreg_p
+generic map (width => data_out_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(data_out_offset to data_out_offset + data_out_q'length-1),
+          scout       => sov(data_out_offset to data_out_offset + data_out_q'length-1),
+          din         => data_out_d,
+          dout        => data_out_q);
+
+
+
+perv_2to1_reg: tri_plat
+  generic map (width => 7, expand_type => expand_type)
+  port map (vd          => vdd,
+            gd          => gnd,
+            nclk        => nclk,
+            flush       => tc_ac_ccflush_dc,
+            din(0)      => pc_iu_func_sl_thold_2,
+            din(1)      => pc_iu_sg_2,
+            din(2)      => pc_iu_time_sl_thold_2,
+            din(3)      => pc_iu_abst_sl_thold_2,
+            din(4)      => pc_iu_ary_nsl_thold_2,
+            din(5)      => pc_iu_repr_sl_thold_2,
+            din(6)      => pc_iu_bolt_sl_thold_2,
+            q(0)        => pc_iu_func_sl_thold_1,
+            q(1)        => pc_iu_sg_1,
+            q(2)        => pc_iu_time_sl_thold_1,
+            q(3)        => pc_iu_abst_sl_thold_1,
+            q(4)        => pc_iu_ary_nsl_thold_1,
+            q(5)        => pc_iu_repr_sl_thold_1,
+            q(6)        => pc_iu_bolt_sl_thold_1
+);
+
+perv_1to0_reg: tri_plat
+  generic map (width => 7, expand_type => expand_type)
+  port map (vd          => vdd,
+            gd          => gnd,
+            nclk        => nclk,
+            flush       => tc_ac_ccflush_dc,
+            din(0)      => pc_iu_func_sl_thold_1,
+            din(1)      => pc_iu_sg_1,
+            din(2)      => pc_iu_time_sl_thold_1,
+            din(3)      => pc_iu_abst_sl_thold_1,
+            din(4)      => pc_iu_ary_nsl_thold_1,
+            din(5)      => pc_iu_repr_sl_thold_1,
+            din(6)      => pc_iu_bolt_sl_thold_1,
+            q(0)        => pc_iu_func_sl_thold_0,
+            q(1)        => pc_iu_sg_0,
+            q(2)        => pc_iu_time_sl_thold_0,
+            q(3)        => pc_iu_abst_sl_thold_0,
+            q(4)        => pc_iu_ary_nsl_thold_0,
+            q(5)        => pc_iu_repr_sl_thold_0,
+            q(6)        => pc_iu_bolt_sl_thold_0
+);
+
+perv_lcbor: tri_lcbor
+  generic map (expand_type => expand_type)
+  port map (clkoff_b    => clkoff_b,
+            thold       => pc_iu_func_sl_thold_0,
+            sg          => pc_iu_sg_0,
+            act_dis     => act_dis,
+            forcee       => forcee,
+            thold_b     => pc_iu_func_sl_thold_0_b);
+
+
+
+siv(0 to scan_right)    <= func_scan_in & sov(0 to scan_right-1);
+func_scan_out           <= sov(scan_right);
+
+
+end tri_bht;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_boltreg_p.vhdl

@@ -0,0 +1,191 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+library ibm; 
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_boltreg_p is
+
+  generic (
+    width       : integer := 4;
+    offset      : integer range 0 to 65535 := 0 ; 
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    sg      : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    scin    : in  std_ulogic_vector(offset to offset+width-1);  
+    din     : in  std_ulogic_vector(offset to offset+width-1);  
+    scout   : out std_ulogic_vector(offset to offset+width-1);
+    dout    : out std_ulogic_vector(offset to offset+width-1) );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_boltreg_p;
+
+architecture tri_boltreg_p of tri_boltreg_p is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+    component c_rlmreg_p
+      generic ( width    : positive  := 4 ;          
+            init     : std_ulogic_vector := "0"; 
+            dualscan : string := ""              
+          );
+    port (
+         nclk        : in  std_ulogic;        
+         act         : in  std_ulogic;        
+         thold_b     : in  std_ulogic;        
+         sg          : in  std_ulogic;        
+         scin        : in  std_ulogic_vector(0 to width-1);  
+         din         : in  std_ulogic_vector(0 to width-1);  
+         dout        : out std_ulogic_vector(0 to width-1);  
+         scout       : out std_ulogic_vector(0 to width-1)   
+       );
+    end component;
+    signal scanin_inv : std_ulogic_vector(0 to width-1);
+    signal scanout_inv : std_ulogic_vector(0 to width-1);
+    signal act_or_force : std_ulogic;
+    signal din_buf : std_ulogic_vector(0 to width-1);
+    signal dout_buf : std_ulogic_vector(0 to width-1);
+  begin
+    act_or_force <= act or forcee;
+
+    cib: 
+    if ibuf = true generate
+      din_buf  <= not din;
+      dout     <= not dout_buf;
+    end generate cib;
+    cnib: 
+    if ibuf = false generate
+      din_buf  <= din;
+      dout     <= dout_buf;
+    end generate cnib;
+
+    l:c_rlmreg_p
+      generic map (width => width, init  => init_v, dualscan => dualscan)
+      port map (
+        nclk    => nclk.clk,
+        act     => act_or_force,
+        thold_b => thold_b,
+        sg      => sg,
+        scin    => scanin_inv,
+        din     => din_buf,
+        scout   => scanout_inv,
+        dout    => dout_buf);
+
+    scanin_inv <= scin xor init_v;
+    scout <= scanout_inv xor init_v;
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+
+    cib: if ibuf = true generate
+      int_din <= (vsreset_b and not din) or
+                 (vsreset and init_v);
+    end generate cib;
+    cnib: if ibuf = false generate
+      int_din <= (vsreset_b and din) or
+                 (vsreset and init_v);
+    end generate cnib;
+
+    vact <= (0 to width-1 => (act or forcee));
+    vact_b <= (0 to width-1 => not (act or forcee));
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+
+    cob: if ibuf = true generate 
+	dout <= not int_dout;
+    end generate cob;
+
+    cnob: if ibuf = false generate 
+	dout <= int_dout;
+    end generate cnob;
+
+    scout <= zeros;
+
+    unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b;
+    unused(1 to width) <= scin;
+  end generate a;
+
+end tri_boltreg_p;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_caa_prism_abist.vhdl

@@ -0,0 +1,145 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee, ibm;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+library support;
+USE support.power_logic_pkg.all;
+library tri;
+use tri.tri_latches_pkg.all;
+
+
+entity tri_caa_prism_abist is
+generic(expand_type     : integer := 1 );    
+Port   (vdd                             : INOUT power_logic;
+        gnd                             : INOUT power_logic;
+        nclk                            : In    clk_logic;
+        scan_dis_dc_b                   : In    std_ulogic;
+        lcb_clkoff_dc_b                 : In    std_ulogic;
+        lcb_mpw1_dc_b                   : In    std_ulogic;
+        lcb_mpw2_dc_b                   : In    std_ulogic;
+        lcb_delay_lclkr_dc              : In    std_ulogic;
+        lcb_delay_lclkr_np_dc           : In    std_ulogic;
+        lcb_act_dis_dc                  : In    std_ulogic;
+        lcb_d_mode_dc                   : In    std_ulogic;
+        gptr_thold                      : In    std_ulogic;
+        gptr_scan_in                    : In    std_ulogic;
+        gptr_scan_out                   : Out   std_ulogic;
+        abist_thold                     : In    std_ulogic;
+        abist_sg                        : In    std_ulogic;
+        abist_scan_in                   : In    std_ulogic;
+        abist_scan_out                  : Out   std_ulogic;
+        abist_done_in_dc                : In    std_ulogic;
+        abist_done_out_dc               : Out   std_ulogic;
+        abist_mode_dc                   : In    std_ulogic;
+        abist_start_test                : In    std_ulogic;
+        lbist_mode_dc                   : In    std_ulogic;
+        lbist_ac_mode_dc                : In    std_ulogic;
+        abist_waddr_0                   : Out   std_ulogic_vector(0 to 9);
+        abist_waddr_1                   : Out   std_ulogic_vector(0 to 9);
+        abist_grf_wenb_0                : Out   std_ulogic;      
+        abist_grf_wenb_1                : Out   std_ulogic;      
+        abist_raddr_0                   : Out   std_ulogic_vector(0 to 9);
+        abist_raddr_1                   : Out   std_ulogic_vector(0 to 9);
+        abist_grf_renb_0                : Out   std_ulogic;
+        abist_grf_renb_1                : Out   std_ulogic;
+        abist_g8t_wenb                  : Out   std_ulogic;
+        abist_g8t1p_renb_0              : Out   std_ulogic;
+        abist_g6t_r_wb                  : Out   std_ulogic;
+        abist_di_g6t_2r                 : Out   std_ulogic_vector(0 to 3);
+        abist_di_0                      : Out   std_ulogic_vector(0 to 3);
+        abist_di_1                      : Out   std_ulogic_vector(0 to 3);
+        abist_dcomp                     : Out   std_ulogic_vector(0 to 3);
+        abist_dcomp_g6t_2r              : Out   std_ulogic_vector(0 to 3);
+        abist_bw_0                      : Out   std_ulogic;
+        abist_bw_1                      : Out   std_ulogic;
+        abist_wl32_g8t_comp_ena         : Out   std_ulogic;
+        abist_wl64_g8t_comp_ena         : Out   std_ulogic;
+        abist_wl128_g8t_comp_ena        : Out   std_ulogic;
+        abist_wl144_comp_ena            : Out   std_ulogic;
+        abist_wl256_comp_ena            : Out   std_ulogic;
+        abist_wl512_comp_ena            : Out   std_ulogic;
+        abist_ena_dc                    : Out   std_ulogic;
+        abist_raw_dc_b                  : Out   std_ulogic
+);
+
+-- synopsys translate_off
+
+
+
+
+-- synopsys translate_on
+end entity tri_caa_prism_abist;
+
+architecture tri_caa_prism_abist of tri_caa_prism_abist is
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+        gptr_scan_out                   <= '0';
+        abist_scan_out                  <= '0';
+        abist_done_out_dc               <= '0';
+        abist_waddr_0                   <= "0000000000";
+        abist_waddr_1                   <= "0000000000";
+        abist_grf_wenb_0                <= '0';      
+        abist_grf_wenb_1                <= '0';      
+        abist_raddr_0                   <= "0000000000";
+        abist_raddr_1                   <= "0000000000";
+        abist_grf_renb_0                <= '0';
+        abist_grf_renb_1                <= '0';
+        abist_g8t_wenb                  <= '0';
+        abist_g8t1p_renb_0              <= '0';
+        abist_g6t_r_wb                  <= '0';
+        abist_di_g6t_2r                 <= "0000";
+        abist_di_0                      <= "0000";
+        abist_di_1                      <= "0000";
+        abist_dcomp                     <= "0000";
+        abist_dcomp_g6t_2r              <= "0000";
+        abist_bw_0                      <= '0';
+        abist_bw_1                      <= '0';
+        abist_wl32_g8t_comp_ena         <= '0';
+        abist_wl64_g8t_comp_ena         <= '0';
+        abist_wl128_g8t_comp_ena        <= '0';
+        abist_wl144_comp_ena            <= '0';
+        abist_wl256_comp_ena            <= '0';
+        abist_wl512_comp_ena            <= '0';
+        abist_ena_dc                    <= '0';
+        abist_raw_dc_b                  <= '0';
+
+        unused <= or_reduce(scan_dis_dc_b & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b &
+                            lcb_delay_lclkr_dc & lcb_delay_lclkr_np_dc & lcb_act_dis_dc & lcb_d_mode_dc &
+                            gptr_thold & gptr_scan_in & abist_thold & abist_sg & abist_scan_in &
+                            abist_done_in_dc & abist_mode_dc & abist_start_test &
+                            lbist_mode_dc & lbist_ac_mode_dc );
+
+end tri_caa_prism_abist;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c_matchline.vhdl

@@ -0,0 +1,396 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all ;
+library ibm;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+
+entity tri_cam_16x143_1r1w1c_matchline is
+  generic (have_xbit : integer := 1;
+             num_pgsizes : integer := 5;
+             have_cmpmask         : integer := 1;
+             cmpmask_width        : integer := 4);
+
+port( 
+    addr_in                          : in std_ulogic_vector(0 to 51);
+    addr_enable                      : in std_ulogic_vector(0 to 1);
+    comp_pgsize                      : in std_ulogic_vector(0 to 2);
+    pgsize_enable                    : in std_ulogic;
+    entry_size                       : in std_ulogic_vector(0 to 2);
+    entry_cmpmask                    : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_xbit                       : in std_ulogic;
+    entry_xbitmask                   : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_epn                        : in std_ulogic_vector(0 to 51);
+    comp_class                       : in std_ulogic_vector(0 to 1);
+    entry_class                      : in std_ulogic_vector(0 to 1);
+    class_enable                     : in std_ulogic_vector(0 to 2);
+    comp_extclass                    : in std_ulogic_vector(0 to 1);
+    entry_extclass                   : in std_ulogic_vector(0 to 1);
+    extclass_enable                  : in std_ulogic_vector(0 to 1);
+    comp_state                       : in std_ulogic_vector(0 to 1);
+    entry_hv                         : in std_ulogic;
+    entry_ds                         : in std_ulogic;
+    state_enable                     : in std_ulogic_vector(0 to 1);
+    entry_thdid                      : in std_ulogic_vector(0 to 3);
+    comp_thdid                       : in std_ulogic_vector(0 to 3);
+    thdid_enable                     : in std_ulogic_vector(0 to 1);
+    entry_pid                        : in std_ulogic_vector(0 to 7);
+    comp_pid                         : in std_ulogic_vector(0 to 7);
+    pid_enable                       : in std_ulogic;
+    entry_v                          : in std_ulogic;
+    comp_invalidate                  : in std_ulogic;
+
+    match                            : out std_ulogic
+);
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end tri_cam_16x143_1r1w1c_matchline;
+
+architecture tri_cam_16x143_1r1w1c_matchline of tri_cam_16x143_1r1w1c_matchline is
+
+
+
+  signal entry_epn_b             : std_ulogic_vector(34 to 51);
+  signal function_50_51     : std_ulogic;
+  signal function_48_51     : std_ulogic;
+  signal function_46_51     : std_ulogic;
+  signal function_44_51     : std_ulogic;
+  signal function_40_51     : std_ulogic;
+  signal function_36_51     : std_ulogic;
+  signal function_34_51     : std_ulogic;
+  signal pgsize_eq_16K  : std_ulogic;
+  signal pgsize_eq_64K  : std_ulogic;
+  signal pgsize_eq_256K : std_ulogic;
+  signal pgsize_eq_1M   : std_ulogic;
+  signal pgsize_eq_16M  : std_ulogic;
+  signal pgsize_eq_256M : std_ulogic;
+  signal pgsize_eq_1G   : std_ulogic;
+  signal pgsize_gte_16K  : std_ulogic;
+  signal pgsize_gte_64K  : std_ulogic;
+  signal pgsize_gte_256K : std_ulogic;
+  signal pgsize_gte_1M   : std_ulogic;
+  signal pgsize_gte_16M  : std_ulogic;
+  signal pgsize_gte_256M : std_ulogic;
+  signal pgsize_gte_1G   : std_ulogic;
+  signal comp_or_34_35      : std_ulogic;
+  signal comp_or_34_39      : std_ulogic;
+  signal comp_or_36_39      : std_ulogic;
+  signal comp_or_40_43      : std_ulogic;
+  signal comp_or_44_45      : std_ulogic;
+  signal comp_or_44_47      : std_ulogic;
+  signal comp_or_46_47      : std_ulogic;
+  signal comp_or_48_49      : std_ulogic;
+  signal comp_or_48_51      : std_ulogic;
+  signal comp_or_50_51      : std_ulogic;
+  signal match_line         : std_ulogic_vector(0 to 72);
+  signal pgsize_match       : std_ulogic;
+  signal addr_match         : std_ulogic;
+  signal class_match        : std_ulogic;
+  signal extclass_match     : std_ulogic;
+  signal state_match        : std_ulogic;
+  signal thdid_match        : std_ulogic;
+  signal pid_match          : std_ulogic;
+
+begin
+
+  match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor
+                             (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3))
+                            );
+
+numpgsz8 : if num_pgsizes = 8 generate
+
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask80 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) );
+  pgsize_eq_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2)));
+  pgsize_eq_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) );
+
+  pgsize_gte_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_gte_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_1G;
+  pgsize_gte_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_256M;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2))) or
+                      pgsize_gte_16M;
+  pgsize_gte_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_256K;
+  pgsize_gte_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_64K;
+
+end generate gen_nocmpmask80;
+
+gen_cmpmask80 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_256M <= not entry_cmpmask(1);
+  pgsize_gte_16M  <= not entry_cmpmask(2);
+  pgsize_gte_1M   <= not entry_cmpmask(3);
+  pgsize_gte_256K <= not entry_cmpmask(4);
+  pgsize_gte_64K  <= not entry_cmpmask(5);
+  pgsize_gte_16K  <= not entry_cmpmask(6);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_256M <= entry_xbitmask(1);
+  pgsize_eq_16M  <= entry_xbitmask(2);
+  pgsize_eq_1M   <= entry_xbitmask(3);
+  pgsize_eq_256K <= entry_xbitmask(4);
+  pgsize_eq_64K  <= entry_xbitmask(5);
+  pgsize_eq_16K  <= entry_xbitmask(6);
+end generate gen_cmpmask80;
+
+gen_noxbit80 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_36_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_46_51 <= '0';
+  function_48_51 <= '0';
+  function_50_51 <= '0';
+end generate gen_noxbit80;
+ 
+gen_xbit80 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_36_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256M) or
+                    or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_46_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256K) or
+                    or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+  function_50_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16K) or
+                    or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51));
+end generate gen_xbit80; 
+
+                    
+
+  comp_or_50_51 <=  and_reduce(match_line(50 to 51)) or pgsize_gte_16K;
+  comp_or_48_49 <=  and_reduce(match_line(48 to 49)) or pgsize_gte_64K;
+  comp_or_46_47 <=  and_reduce(match_line(46 to 47)) or pgsize_gte_256K;
+  comp_or_44_45 <=  and_reduce(match_line(44 to 45)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_36_39 <=  and_reduce(match_line(36 to 39)) or pgsize_gte_256M;
+  comp_or_34_35 <=  and_reduce(match_line(34 to 35)) or pgsize_gte_1G;
+
+gen_noxbit81 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit81;
+ 
+gen_xbit81 : if have_xbit /= 0 generate
+  addr_match <=    (function_50_51 and               
+                    function_48_51 and
+                    function_46_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_36_51 and
+                    function_34_51 and
+                    comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit81; 
+
+end generate numpgsz8; 
+
+
+numpgsz5 : if num_pgsizes = 5 generate
+
+  function_50_51 <= '0';
+  function_46_51 <= '0';
+  function_36_51 <= '0';
+  pgsize_eq_16K <= '0';
+  pgsize_eq_256K <= '0';
+  pgsize_eq_256M <= '0';
+  pgsize_gte_16K <= '0';
+  pgsize_gte_256K <= '0';
+  pgsize_gte_256M <= '0';
+  comp_or_34_35 <= '0';
+  comp_or_36_39 <= '0';
+  comp_or_44_45 <= '0';
+  comp_or_46_47 <= '0';
+  comp_or_48_49 <= '0';
+  comp_or_50_51 <= '0';
+  
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask50 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+  pgsize_eq_16M   <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) );
+  pgsize_eq_1M    <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2));
+  pgsize_eq_64K   <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2));
+  
+
+  pgsize_gte_1G  <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+
+  pgsize_gte_16M  <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1G;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2)) or
+                      pgsize_gte_16M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2)) or
+                      pgsize_gte_1M;
+end generate gen_nocmpmask50;
+
+gen_cmpmask50 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_16M  <= not entry_cmpmask(1);
+  pgsize_gte_1M   <= not entry_cmpmask(2);
+  pgsize_gte_64K  <= not entry_cmpmask(3);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_16M  <= entry_xbitmask(1);
+  pgsize_eq_1M   <= entry_xbitmask(2);
+  pgsize_eq_64K  <= entry_xbitmask(3);
+end generate gen_cmpmask50;
+
+gen_noxbit50 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_48_51 <= '0';
+end generate gen_noxbit50;
+ 
+gen_xbit50 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+end generate gen_xbit50;
+
+  comp_or_48_51 <=  and_reduce(match_line(48 to 51)) or pgsize_gte_64K;
+  comp_or_44_47 <=  and_reduce(match_line(44 to 47)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_34_39 <=  and_reduce(match_line(34 to 39)) or pgsize_gte_1G;
+
+gen_noxbit51 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit51;
+
+gen_xbit51 : if have_xbit /= 0 generate
+  addr_match <=    (function_48_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_34_51 and
+                    comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit51;
+
+end generate numpgsz5; 
+
+
+  pgsize_match <=   and_reduce(match_line(52 to 54)) or
+                    not(pgsize_enable);
+
+  class_match  <=  (match_line(55) or not(class_enable(0))) and 
+                    (match_line(56) or not(class_enable(1))) and 
+                    (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  extclass_match <= (match_line(57) or not(extclass_enable(0))) and  
+                     (match_line(58) or not(extclass_enable(1)));     
+
+  state_match <=    (match_line(59) or
+                     not(state_enable(0))) and
+                     (match_line(60) or
+                     not(state_enable(1)));
+
+  thdid_match <=   (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and 
+                    (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  pid_match <=      and_reduce(match_line(61 to 68)) or
+                    (not(entry_extclass(1)) and not comp_invalidate) or  
+                      not(pid_enable); 
+
+  match <=         addr_match and                       
+                    pgsize_match and                     
+                    class_match and                      
+                    extclass_match and                   
+                    state_match and                      
+                    thdid_match and                      
+                    pid_match and                        
+                    entry_v;                             
+
+end tri_cam_16x143_1r1w1c_matchline;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c_matchline.vhdl

@@ -0,0 +1,398 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all ;
+library ibm;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+
+entity tri_cam_32x143_1r1w1c_matchline is
+  generic (have_xbit : integer := 1;
+             num_pgsizes : integer := 5;
+             have_cmpmask         : integer := 1;
+             cmpmask_width        : integer := 4);
+
+port( 
+    addr_in                          : in std_ulogic_vector(0 to 51);
+    addr_enable                      : in std_ulogic_vector(0 to 1);
+    comp_pgsize                      : in std_ulogic_vector(0 to 2);
+    pgsize_enable                    : in std_ulogic;
+    entry_size                       : in std_ulogic_vector(0 to 2);
+    entry_cmpmask                    : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_xbit                       : in std_ulogic;
+    entry_xbitmask                   : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_epn                        : in std_ulogic_vector(0 to 51);
+    comp_class                       : in std_ulogic_vector(0 to 1);
+    entry_class                      : in std_ulogic_vector(0 to 1);
+    class_enable                     : in std_ulogic_vector(0 to 2);
+    comp_extclass                    : in std_ulogic_vector(0 to 1);
+    entry_extclass                   : in std_ulogic_vector(0 to 1);
+    extclass_enable                  : in std_ulogic_vector(0 to 1);
+    comp_state                       : in std_ulogic_vector(0 to 1);
+    entry_hv                         : in std_ulogic;
+    entry_ds                         : in std_ulogic;
+    state_enable                     : in std_ulogic_vector(0 to 1);
+    entry_thdid                      : in std_ulogic_vector(0 to 3);
+    comp_thdid                       : in std_ulogic_vector(0 to 3);
+    thdid_enable                     : in std_ulogic_vector(0 to 1);
+    entry_pid                        : in std_ulogic_vector(0 to 7);
+    comp_pid                         : in std_ulogic_vector(0 to 7);
+    pid_enable                       : in std_ulogic;
+    entry_v                          : in std_ulogic;
+    comp_invalidate                  : in std_ulogic;
+
+    match                            : out std_ulogic
+);
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end tri_cam_32x143_1r1w1c_matchline;
+
+architecture tri_cam_32x143_1r1w1c_matchline of tri_cam_32x143_1r1w1c_matchline is
+
+
+
+  signal entry_epn_b             : std_ulogic_vector(34 to 51);
+  signal function_50_51     : std_ulogic;
+  signal function_48_51     : std_ulogic;
+  signal function_46_51     : std_ulogic;
+  signal function_44_51     : std_ulogic;
+  signal function_40_51     : std_ulogic;
+  signal function_36_51     : std_ulogic;
+  signal function_34_51     : std_ulogic;
+  signal pgsize_eq_16K  : std_ulogic;
+  signal pgsize_eq_64K  : std_ulogic;
+  signal pgsize_eq_256K : std_ulogic;
+  signal pgsize_eq_1M   : std_ulogic;
+  signal pgsize_eq_16M  : std_ulogic;
+  signal pgsize_eq_256M : std_ulogic;
+  signal pgsize_eq_1G   : std_ulogic;
+  signal pgsize_gte_16K  : std_ulogic;
+  signal pgsize_gte_64K  : std_ulogic;
+  signal pgsize_gte_256K : std_ulogic;
+  signal pgsize_gte_1M   : std_ulogic;
+  signal pgsize_gte_16M  : std_ulogic;
+  signal pgsize_gte_256M : std_ulogic;
+  signal pgsize_gte_1G   : std_ulogic;
+  signal comp_or_34_35      : std_ulogic;
+  signal comp_or_34_39      : std_ulogic;
+  signal comp_or_36_39      : std_ulogic;
+  signal comp_or_40_43      : std_ulogic;
+  signal comp_or_44_45      : std_ulogic;
+  signal comp_or_44_47      : std_ulogic;
+  signal comp_or_46_47      : std_ulogic;
+  signal comp_or_48_49      : std_ulogic;
+  signal comp_or_48_51      : std_ulogic;
+  signal comp_or_50_51      : std_ulogic;
+  signal match_line         : std_ulogic_vector(0 to 72);
+  signal pgsize_match       : std_ulogic;
+  signal addr_match         : std_ulogic;
+  signal class_match        : std_ulogic;
+  signal extclass_match     : std_ulogic;
+  signal state_match        : std_ulogic;
+  signal thdid_match        : std_ulogic;
+  signal pid_match          : std_ulogic;
+
+begin
+
+  match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor
+                             (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3))
+                            );
+
+numpgsz8 : if num_pgsizes = 8 generate
+
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask80 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) );
+  pgsize_eq_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2)));
+  pgsize_eq_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) );
+
+  pgsize_gte_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_gte_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_1G;
+  pgsize_gte_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_256M;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2))) or
+                      pgsize_gte_16M;
+  pgsize_gte_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_256K;
+  pgsize_gte_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_64K;
+
+
+end generate gen_nocmpmask80;
+
+gen_cmpmask80 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_256M <= not entry_cmpmask(1);
+  pgsize_gte_16M  <= not entry_cmpmask(2);
+  pgsize_gte_1M   <= not entry_cmpmask(3);
+  pgsize_gte_256K <= not entry_cmpmask(4);
+  pgsize_gte_64K  <= not entry_cmpmask(5);
+  pgsize_gte_16K  <= not entry_cmpmask(6);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_256M <= entry_xbitmask(1);
+  pgsize_eq_16M  <= entry_xbitmask(2);
+  pgsize_eq_1M   <= entry_xbitmask(3);
+  pgsize_eq_256K <= entry_xbitmask(4);
+  pgsize_eq_64K  <= entry_xbitmask(5);
+  pgsize_eq_16K  <= entry_xbitmask(6);
+end generate gen_cmpmask80;
+
+gen_noxbit80 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_36_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_46_51 <= '0';
+  function_48_51 <= '0';
+  function_50_51 <= '0';
+end generate gen_noxbit80;
+ 
+gen_xbit80 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_36_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256M) or
+                    or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_46_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256K) or
+                    or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+  function_50_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16K) or
+                    or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51));
+end generate gen_xbit80; 
+                    
+
+  comp_or_50_51 <=  and_reduce(match_line(50 to 51)) or pgsize_gte_16K;
+  comp_or_48_49 <=  and_reduce(match_line(48 to 49)) or pgsize_gte_64K;
+  comp_or_46_47 <=  and_reduce(match_line(46 to 47)) or pgsize_gte_256K;
+  comp_or_44_45 <=  and_reduce(match_line(44 to 45)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_36_39 <=  and_reduce(match_line(36 to 39)) or pgsize_gte_256M;
+  comp_or_34_35 <=  and_reduce(match_line(34 to 35)) or pgsize_gte_1G;
+
+gen_noxbit81 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit81;
+ 
+gen_xbit81 : if have_xbit /= 0 generate
+  addr_match <=    (function_50_51 and               
+                    function_48_51 and
+                    function_46_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_36_51 and
+                    function_34_51 and
+                    comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit81; 
+
+end generate numpgsz8; 
+
+
+numpgsz5 : if num_pgsizes = 5 generate
+
+  function_50_51 <= '0';
+  function_46_51 <= '0';
+  function_36_51 <= '0';
+  pgsize_eq_16K <= '0';
+  pgsize_eq_256K <= '0';
+  pgsize_eq_256M <= '0';
+  pgsize_gte_16K <= '0';
+  pgsize_gte_256K <= '0';
+  pgsize_gte_256M <= '0';
+  comp_or_34_35 <= '0';
+  comp_or_36_39 <= '0';
+  comp_or_44_45 <= '0';
+  comp_or_46_47 <= '0';
+  comp_or_48_49 <= '0';
+  comp_or_50_51 <= '0';
+  
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask50 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+  pgsize_eq_16M   <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) );
+  pgsize_eq_1M    <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2));
+  pgsize_eq_64K   <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2));
+  
+
+  pgsize_gte_1G  <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+
+  pgsize_gte_16M  <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1G;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2)) or
+                      pgsize_gte_16M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2)) or
+                      pgsize_gte_1M;
+
+end generate gen_nocmpmask50;
+
+gen_cmpmask50 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_16M  <= not entry_cmpmask(1);
+  pgsize_gte_1M   <= not entry_cmpmask(2);
+  pgsize_gte_64K  <= not entry_cmpmask(3);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_16M  <= entry_xbitmask(1);
+  pgsize_eq_1M   <= entry_xbitmask(2);
+  pgsize_eq_64K  <= entry_xbitmask(3);
+end generate gen_cmpmask50;
+
+gen_noxbit50 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_48_51 <= '0';
+end generate gen_noxbit50;
+ 
+gen_xbit50 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+end generate gen_xbit50;
+
+  comp_or_48_51 <=  and_reduce(match_line(48 to 51)) or pgsize_gte_64K;
+  comp_or_44_47 <=  and_reduce(match_line(44 to 47)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_34_39 <=  and_reduce(match_line(34 to 39)) or pgsize_gte_1G;
+
+gen_noxbit51 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit51;
+
+gen_xbit51 : if have_xbit /= 0 generate
+  addr_match <=    (function_48_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_34_51 and
+                    comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit51;
+
+end generate numpgsz5; 
+
+
+  pgsize_match <=   and_reduce(match_line(52 to 54)) or
+                    not(pgsize_enable);
+
+  class_match  <=  (match_line(55) or not(class_enable(0))) and 
+                    (match_line(56) or not(class_enable(1))) and 
+                    (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  extclass_match <= (match_line(57) or not(extclass_enable(0))) and  
+                     (match_line(58) or not(extclass_enable(1)));     
+
+  state_match <=    (match_line(59) or
+                     not(state_enable(0))) and
+                     (match_line(60) or
+                     not(state_enable(1)));
+
+  thdid_match <=   (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and 
+                    (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  pid_match <=      and_reduce(match_line(61 to 68)) or
+                    (not(entry_extclass(1)) and not comp_invalidate) or  
+                      not(pid_enable); 
+
+  match <=         addr_match and                       
+                    pgsize_match and                     
+                    class_match and                      
+                    extclass_match and                   
+                    state_match and                      
+                    thdid_match and                      
+                    pid_match and                        
+                    entry_v;                             
+
+
+end tri_cam_32x143_1r1w1c_matchline;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_parerr_mac.vhdl

@@ -0,0 +1,178 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;
+use ieee.std_logic_1164.all;
+library ibm;
+use ibm.std_ulogic_unsigned.all;
+use ibm.std_ulogic_function_support.all;
+library support;
+use support.power_logic_pkg.all;
+library tri;
+use tri.tri_latches_pkg.all;
+
+entity tri_cam_parerr_mac  is
+  generic (expand_type : integer := 1);
+  port(
+
+   np1_cam_cmp_data             :in  std_ulogic_vector(0 to 83);
+   np1_array_cmp_data           :in  std_ulogic_vector(0 to 67);
+
+   np2_cam_cmp_data             :out std_ulogic_vector(0 to 83);
+   np2_array_cmp_data           :out std_ulogic_vector(0 to 67);
+   np2_cmp_data_parerr_epn      :out std_ulogic; 
+   np2_cmp_data_parerr_rpn      :out std_ulogic;
+
+   gnd                          :inout power_logic;
+   vdd                          :inout power_logic;
+   nclk                         :in  clk_logic;
+   act                          :in  std_ulogic;
+   lcb_act_dis_dc               :in  std_ulogic;
+   lcb_delay_lclkr_dc           :in  std_ulogic;
+   lcb_clkoff_dc_b_0            :in  std_ulogic;
+   lcb_mpw1_dc_b                :in  std_ulogic;
+   lcb_mpw2_dc_b                :in  std_ulogic;
+   lcb_sg_0                     :in  std_ulogic;
+   lcb_func_sl_thold_0          :in  std_ulogic; 
+   func_scan_in                 :in  std_ulogic;
+   func_scan_out                :out std_ulogic
+  );
+-- synopsys translate_off
+-- synopsys translate_on
+end entity tri_cam_parerr_mac;
+
+architecture tri_cam_parerr_mac of tri_cam_parerr_mac is
+
+begin
+
+  um: if expand_type = 0 generate
+      signal np2_cam_cmp_data_q         :std_ulogic_vector(0 to np1_cam_cmp_data'length-1);
+      signal np2_array_cmp_data_q       :std_ulogic_vector(0 to np1_array_cmp_data'length-1);
+      signal np2_cmp_data_calc_par      :std_ulogic_vector(50 to 67);
+
+  begin
+      np1_cam_cmp_data_latch: tri_rlmreg_p
+        generic map (width => np1_cam_cmp_data'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => np1_cam_cmp_data,
+                  dout        => np2_cam_cmp_data_q);
+
+      np1_array_cmp_data_latch: tri_rlmreg_p
+        generic map (width => np1_array_cmp_data'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => np1_array_cmp_data,
+                  dout        => np2_array_cmp_data_q);
+
+      np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82));
+      np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7));
+      np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15));
+      np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23));
+      np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31));
+      np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39));
+      np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47));
+      np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55));
+      np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62));
+      np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66));
+      np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74));
+      np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5));
+      np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13));
+      np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21));
+      np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29));
+      np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37));
+      np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44));
+      np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50));
+
+      np2_cmp_data_parerr_epn   <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60)));
+      np2_cmp_data_parerr_rpn   <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67));
+      np2_cam_cmp_data          <= np2_cam_cmp_data_q;
+      np2_array_cmp_data        <= np2_array_cmp_data_q;
+  end generate um;
+
+  a: if expand_type = 1 generate
+      signal np2_cam_cmp_data_q         :std_ulogic_vector(0 to np1_cam_cmp_data'length-1);
+      signal np2_array_cmp_data_q       :std_ulogic_vector(0 to np1_array_cmp_data'length-1);
+      signal np2_cmp_data_calc_par      :std_ulogic_vector(50 to 67);
+      signal clk                        :std_ulogic;
+      signal sreset_q                   :std_ulogic;
+  begin
+     clk   <= not nclk.clk;
+     rlatch: process (clk)
+     begin
+       if(rising_edge(clk)) then
+         sreset_q             <= nclk.sreset;
+       end if;
+     end process;
+
+     slatch: process (nclk,sreset_q)
+     begin
+       if(rising_edge(nclk.clk)) then
+         if (sreset_q = '1') then
+           np2_cam_cmp_data_q   <= (others=>'0');
+           np2_array_cmp_data_q <= (others=>'0');
+         else
+           np2_cam_cmp_data_q   <= np1_cam_cmp_data;
+           np2_array_cmp_data_q <= np1_array_cmp_data;
+         end if;
+       end if;
+     end process;
+
+     np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82));
+     np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7));
+     np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15));
+     np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23));
+     np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31));
+     np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39));
+     np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47));
+     np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55));
+     np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62));
+     np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66));
+     np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74));
+     np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5));
+     np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13));
+     np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21));
+     np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29));
+     np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37));
+     np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44));
+     np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50));
+
+     np2_cmp_data_parerr_epn   <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60)));
+     np2_cmp_data_parerr_rpn   <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67));
+     np2_cam_cmp_data          <= np2_cam_cmp_data_q;
+     np2_array_cmp_data        <= np2_array_cmp_data_q;
+
+     func_scan_out <= func_scan_in;
+  end generate a;
+
+end tri_cam_parerr_mac;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_direct_err_rpt.vhdl

@@ -0,0 +1,66 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support;                  use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_direct_err_rpt is
+
+  generic (
+      width         : positive := 1 ;      
+      expand_type   : integer  := 1 );     
+  port (
+      vd            : inout power_logic;
+      gd            : inout power_logic;
+
+      err_in        : in  std_ulogic_vector(0 to width-1);
+      err_out       : out std_ulogic_vector(0 to width-1)
+  );
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end tri_direct_err_rpt;
+
+architecture tri_direct_err_rpt of tri_direct_err_rpt is
+
+begin  
+
+  a: if expand_type /= 2 generate
+  begin
+    err_out <= err_in;
+  end generate a;
+
+end tri_direct_err_rpt;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_err_rpt.vhdl

@@ -0,0 +1,132 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+