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147 lines
5.8 KiB
VHDL
147 lines
5.8 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,support,ibm;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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entity c_event_mux is
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generic( events_in : integer := 32;
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events_out : integer := 8 );
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port(
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vd : inout power_logic;
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gd : inout power_logic;
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t0_events : in std_ulogic_vector(0 to events_in/4-1);
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t1_events : in std_ulogic_vector(0 to events_in/4-1);
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t2_events : in std_ulogic_vector(0 to events_in/4-1);
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t3_events : in std_ulogic_vector(0 to events_in/4-1);
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select_bits : in std_ulogic_vector(0 to ((events_in/64+4)*events_out)-1);
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event_bits : out std_ulogic_vector(0 to events_out-1)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end c_event_mux;
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architecture c_event_mux of c_event_mux is
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constant INCR : natural := events_in/64+4;
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constant SIZE : natural := events_in/64+1;
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signal inMuxDec : std_ulogic_vector(0 to events_out*events_in/4-1);
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signal inMuxOut : std_ulogic_vector(0 to events_out*events_in/4-1);
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signal thrd_sel : std_ulogic_vector(0 to events_out-1);
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signal inMux_sel : std_ulogic_vector(0 to ((events_in/64+3)*events_out)-1);
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begin
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thrd_sel <= select_bits(0*INCR) & select_bits(1*INCR) &
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select_bits(2*INCR) & select_bits(3*INCR) &
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select_bits(4*INCR) & select_bits(5*INCR) &
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select_bits(6*INCR) & select_bits(7*INCR) ;
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inMux_sel <= select_bits(0*INCR+1 to (0+1)*INCR-1) &
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select_bits(1*INCR+1 to (1+1)*INCR-1) &
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select_bits(2*INCR+1 to (2+1)*INCR-1) &
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select_bits(3*INCR+1 to (3+1)*INCR-1) &
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select_bits(4*INCR+1 to (4+1)*INCR-1) &
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select_bits(5*INCR+1 to (5+1)*INCR-1) &
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select_bits(6*INCR+1 to (6+1)*INCR-1) &
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select_bits(7*INCR+1 to (7+1)*INCR-1) ;
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decode: for X in 0 to events_out-1 generate
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Mux32: if (events_in = 32) generate
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inMuxDec(X*events_in/4 to X*events_in/4+7) <= decode_3to8(inMux_sel(X*3 to X*3+2));
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end generate Mux32;
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Mux64: if (events_in = 64) generate
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inMuxDec(X*events_in/4 to X*events_in/4+15) <= decode_4to16(inMux_sel(X*4 to X*4+3));
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end generate Mux64;
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Mux128: if (events_in = 128) generate
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inMuxDec(X*events_in/4 to X*events_in/4+31) <= decode_5to32(inMux_sel(X*5 to X*5+4));
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end generate Mux128;
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end generate decode;
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inpMuxHi: for X in 0 to events_out/2-1 generate
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eventSel: for I in 0 to events_in/4-1 generate
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inMuxOut(X*events_in/4 + I) <=
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((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t0_events(I)) or
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(inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t1_events(I)) );
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end generate eventSel;
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end generate inpMuxHi;
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inpMuxLo: for X in events_out/2 to events_out-1 generate
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eventSel: for I in 0 to events_in/4-1 generate
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inMuxOut(X*events_in/4 + I) <=
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((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t2_events(I)) or
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(inMuxDec(X*events_in/4 + I) and thrd_sel(X) and t3_events(I)) );
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end generate eventSel;
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end generate inpMuxLo;
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bitOutHi: for X in 0 to events_out/2-1 generate
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Mux32: if (events_in = 32) generate
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event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
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end generate Mux32;
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Mux64: if (events_in = 64) generate
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event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
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end generate Mux64;
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Mux128: if (events_in = 128) generate
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event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
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end generate Mux128;
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end generate bitOutHi;
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bitOutLo: for X in events_out/2 to events_out-1 generate
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Mux32: if (events_in = 32) generate
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event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
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end generate Mux32;
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Mux64: if (events_in = 64) generate
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event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
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end generate Mux64;
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Mux128: if (events_in = 128) generate
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event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
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end generate Mux128;
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end generate bitOutLo;
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end c_event_mux;
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