openpower.foundation/content/blog/parallelware-technology-eas...

37 lines
3.0 KiB
Markdown

This file contains invisible Unicode characters!

This file contains invisible Unicode characters that may be processed differently from what appears below. If your use case is intentional and legitimate, you can safely ignore this warning. Use the Escape button to reveal hidden characters.

This file contains ambiguous Unicode characters that may be confused with others in your current locale. If your use case is intentional and legitimate, you can safely ignore this warning. Use the Escape button to highlight these characters.

---
title: "How Parallelware Technology Eases HPC Software Development for POWER Systems"
date: "2019-01-22"
categories:
- "blogs"
tags:
- "featured"
---
_Featuring OpenPOWER member: [Appentra](https://www.appentra.com/)_
By [Ganesan Narayanasamy](https://www.linkedin.com/in/ganesannarayanasamy/), senior technical computing solution and client care manager, IBM
The 3rd OpenPOWER Academic Discussion Group Workshop was a great meeting of more than 40 developers, researchers and partners all working on Power. Ive already summarized two sessions led by speakers from Oak Ridge National Laboratory [Early Application Experiences on Summit](https://openpowerfoundation.org/blogs/early-application-experiences-summit-oak-ridge/) and [Targeting GPUs using OpenMP Directives on Summit](https://openpowerfoundation.org/blogs/targeting-gpus-using-openmp-directives/).
[Manuel Arenaz](https://www.linkedin.com/in/manuelarenaz/), CEO and co-founder of [Appentra](https://www.appentra.com/), led a session designed to answer an important question: is there a need for parallelware tools on POWER systems? According to Arenaz, there is of course incredible computational power in even a single node of a Power-based supercomputer like [Summit](https://www.olcf.ornl.gov/summit/). But there are also a number of parallel programming challenges:
- Parallel programming of many-core processors
- Parallel programming of multiple GPUs
- Data movement through a heterogeneous complex memory hierarchy
- Training of computational researchers and engineers
- Porting of existing codes to pre-exascale systems
Appentras efforts to make code parallel and help developers make the most of high performance computing resources can help solve these challenges. [Parallelware Trainer](https://www.appentra.com/products/parallelware-trainer/) is an interactive tool that acts as a virtual mentor to provide faster, more effective learning. And [Parallelware Analyzer](https://www.appentra.com/products/parallelware-analyzer/) (still in beta) is a command-line reporting tool to improve productivity of HPC application developers.
Appentra plans to certify both Parallelware tools as [OpenPOWER Ready](https://openpowerfoundation.org/technical/openpower-ready/) in 2019.
For more detail on the product roadmap of Parallelware Trainer and Parallelware Analyzer, view Arenaz full session video and slides below.
https://www.youtube.com/watch?v=6unHYjQruEg
 
<iframe style="border: 1px solid #CCC; border-width: 1px; margin-bottom: 5px; max-width: 100%;" src="//www.slideshare.net/slideshow/embed_code/key/LFrg0y165DM5zN" width="595" height="485" frameborder="0" marginwidth="0" marginheight="0" scrolling="no" allowfullscreen="allowfullscreen"></iframe>
**[How Parallelware technology eases HPC software development for POWER systems](//www.slideshare.net/ganesannarayanasamy/how-parallelware-technology-eases-hpc-software-development-for-power-systems "How Parallelware technology eases HPC software development for POWER systems")** from **[Ganesan Narayanasamy](https://www.slideshare.net/ganesannarayanasamy)**