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jamesk-pat
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 James Kulina
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44a15e1ff8 | 3 years ago |
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---
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title: Virginia Tech opens up MIPS and POWER based Computer Architecture Curriculum
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categories:
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- blogs
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tags:
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- openpower
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- openpower-foundation
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- linux-foundation
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- open-source
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- Virginia Tech
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- Curriculum
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- Computer Architecture
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date: 2022-09-14
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draft: true
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---
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Today, we are pleased to announce that MIPS and POWER based computer architecture curriculum developed by Dr. Wu Feng of Virginia Tech has been released publicly as open source.
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https://github.com/w-feng/CompArch-MIPS-POWER
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---
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title: Blogs
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outputs:
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- html
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- rss
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- json
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date: 2022-01-31
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draft: false
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---
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---
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title: "Advancing the Human Brain Project with OpenPOWER"
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date: "2016-10-27"
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categories:
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- "blogs"
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tags:
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- "featured"
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---
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_By Dr. Dirk Pleiter, Research Group Leader, Jülich Supercomputing Centre_
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The [Human Brain Project](https://www.humanbrainproject.eu/) (HBP), a flagship project [funded by the European Commission](http://ec.europa.eu/research/fp7/index_en.cfm), has set itself an ambitious goal: Unifying our understanding of the human brain. To achieve it, researchers need a High-Performance Analytics and Compute Platform comprised of supercomputers with features that are currently not available, but OpenPOWER is working to make them a reality.
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Through a Pre-Commercial Procurement (PCP) the HBP initiated the necessary R&D, and turned to the OpenPOWER Foundation for help. During three consecutive phases, a consortium of [IBM and NVIDIA has successfully been awarded with R&D contracts](http://www.fz-juelich.de/SharedDocs/Pressemitteilungen/UK/EN/2016/16-09-27hbp_pilotsysteme.html). As part of this effort, a pilot system called [JURON](https://hbp-hpc-platform.fz-juelich.de/?page_id=1073) (a combination of Jülich and neuron) has been installed at Jülich Supercomputing Centre (JSC). It is based on the [new IBM S822LC for HPC servers](https://www.ibm.com/blogs/systems/ibm-nvidia-present-nvlink-server-youve-waiting/), each equipped with two POWER8 processors and four NVIDIA P100 GPUs.
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Marcel Huysegoms, a scientist from [the Institute for Neuroscience and Medicine](http://www.fz-juelich.de/inm/EN/Home/home_node.html), with support from the JSC could demonstrate soon after deployment the usability of the system for his brain image registration application. Exploiting the processing capabilities of the GPUs without further tuning, could achieve a significant speed-up compared to the currently used production system based on Haswell x86 processors and K80 GPUs.
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Not only do the improved compute capabilities matter for brain research, but also by designing and implementing the Global Sharing Layer (GSL), the non-volatile memory cards mounted on all nodes became a byte addressable, globally accessible memory resource. Using JURON it could be shown that data can be read at a rate that is only limited by network performance. These new technologies will open new opportunities for enabling data-intensive workflows in brain research, including data visualization.
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The pilot system will be the first system based on POWER processors where graphics support is being brought to the HPC node. In combination with the GSL it will be possible to visualize large data volumes that are, as an example, generated by brain model simulations. Flexible allocation of resources to compute applications, data analytics and visualization pipelines will be facilitated through another new component, namely the dynamic resource management. It allows for suspension of execution of parallel jobs for a later restart with a different number of processes.
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JURON clearly demonstrates the potential of a technology ecosystem settled around a processor architecture with interfaces that facilitate efficient integration of various devices for efficient processing, moving and storing of data. In other words, it demonstrates the collaborative potential of OpenPOWER.
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---
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title: "Algo-Logic Systems launches CAPI enabled Order Book running on IBM® POWER8™ server"
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date: "2015-03-18"
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categories:
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- "press-releases"
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- "blogs"
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---
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SANTA CLARA, Calif., March 16, 2015 /PRNewswire/ -- Algo-Logic Systems, a recognized leader in providing hardware-accelerated, deterministic, ultra-low-latency products, systems and solutions for accelerated finance, packet processing and embedded system industries, announced today availability of their new Coherent Accelerator Processor Interface (CAPI) enabled Full Order Book solution on IBM® POWER8™ systems. The CAPI enabled Order Book performs all feed processing and book building in logic inside a single Stratix V FPGA on the Nallatech P385 card. The system enables software to directly receive order book snapshots in the coherent shared memory with the least possible latency. The low latency Order Book is designed using the on-chip memory for customer book sizes with many thousands of open orders, up to 24 symbols, and reporting of six L-2 book levels. For use cases where millions of open orders and full market depth need to be tracked, the scalable CAPI enabled Order Book is still implemented with a single FPGA but stores data in off-chip memory.
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Photo - [http://photos.prnewswire.com/prnh/20150314/181760](http://photos.prnewswire.com/prnh/20150314/181760)
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The CAPI Order Book building process includes (i) receiving parsed market data feed messages, (ii) building and maintaining L-3 order-level replica of the exchange's displayable book, (iii) building L-2 books for each symbol with the market depth and weight summary of all open orders, (iv) reporting locally generated copy of the top-of-book with configurable amount of market depth (L-2 snapshots) as well as the last trade information when orders execute. By using the IBM POWER8 server, algorithms can run on the highest number of cores and seamlessly integrate with the Order Book hardware accelerator by means of the coherent shared memory. Through simple memory-mapped IO (MMIO) address space, all the parameters are configurable and statistics can be easily read from software. Algo-Logic's CAPI enabled Full Order Book achieves deterministic, ultra-low-latency without jitter regardless of the number of tracked symbols at data rates of up to 10 Gbps. Key features include:
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- Accelerated Function Unit (AFU) is implemented on FPGA under CAPI
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- Full Order Book with a L-2 default size of 6 price-levels per symbol, fully scalable to larger sizes
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- By default L-2 snapshots are generated for each symbol
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- The number of symbols in use and their respective snapshots are user configurable
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- L-2 snapshot generation frequency is also user configurable on an event basis or at a customizable interval
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- Full Order Book with a L-2 default size of 6 price-levels per symbol, fully scalable to larger sizes
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- By default L-2 snapshots are generated for each symbol
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- The number of symbols in use and their respective snapshots are user configurable
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- L-2 snapshot generation frequency is also user configurable on an event basis or at a customizable interval
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- Full Order Book output logic seamlessly connects to customer's proprietary algorithmic trading strategies
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- Trader has access to the latest market depth (L-2 snapshots) in coherent shared memory
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- L-3 Book updates complete with processing latency of less than 230 nanoseconds
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- L-2 Book updates complete with processing latency of less than 120 nanoseconds
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The CAPI Order Book can be seamlessly integrated with other components of Algo-Logic's Low Latency Application Library, including pre-built protocol parsing libraries, market data filters, and TCP/IP endpoints to deploy complete tick-to-trade applications within a single Stratix V FPGA platform.
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Algo-Logic's world-class hardware accelerated systems and solutions are used by banks, trading firms, market makers, hedge-funds, and financial institutions to accelerate their network processing for protocol parsing, symbol filtering, Risk-Checks (sec 15c 3-5), order book processing, order injection, proprietary trading strategies, high frequency trading, financial surveillance systems, and algorithmic trading.
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Availability: The CAPI Order Book solution is currently shipping, for additional information please contact [Info@algo-logic.com](mailto:Info@algo-logic.com) or visit our website at: [www.algo-logic.com](http://www.algo-logic.com/)
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About Algo-Logic Systems Algo-Logic Systems, Inc., is the recognized leader and developer of Gateware Defined Networking® (GDN) for Field Programmable Gate Array (FPGA) devices. Algo-Logic IP-Cores are used for accelerated finance, packet processing and classification in datacenters, and real-time data acquisition and processing in embedded hardware systems. The company has extensive experience in building complete network processing system solutions in FPGA logic.
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To view the original version on PR Newswire, visit:[http://www.prnewswire.com/news-releases/algo-logic-systems-launches-capi-enabled-order-book-running-on-ibm-power8-server-300050631.html](http://www.prnewswire.com/news-releases/algo-logic-systems-launches-capi-enabled-order-book-running-on-ibm-power8-server-300050631.html)
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SOURCE Algo-Logic Systems
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---
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title: "AMI Joins OpenPOWER"
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date: "2015-06-03"
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categories:
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- "press-releases"
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- "blogs"
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---
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---
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title: "Blog | IT powers new business models"
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date: "2014-07-02"
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categories:
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- "blogs"
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---
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People and businesses today are rapidly adopting new technologies and devices that are transforming the way they interact with each other and their data.
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This digital transformation generates 2.5 quintillion bytes of data associated with the proliferation of mobile devices, social media and cloud computing, and drives tremendous growth opportunity.
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title: "Canonical Supporting IBM POWER8 for Ubuntu Cloud, Big Data"
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date: "2014-06-27"
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categories:
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- "blogs"
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If Ubuntu Linux is to prove truly competitive in theOpenStack cloud and Big Data worlds, it needs to run on more than x86 hardware. And that's whatCanonical achieved this month, with the announcement of full support for IBM POWER8machines on Ubuntu Cloud and Ubuntu Server.
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title: "Center of Accelerated Application Readiness: Preparing applications for Summit"
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date: "2015-03-18"
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categories:
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- "blogs"
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---
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### Abstract
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The hybrid CPU-GPU architecture is one of the main tracks for dealing with the power limitations imposed on high performance computing systems. It is expected that large leadership computing facilities will, for the foreseeable future, deploy systems with this design to address science and engineering challenges for government, academia, and industry. Consistent with this trend, the U.S. Department of Energy's (DOE) Oak Ridge Leadership Computing Facility (OLCF) has signed a contract with IBM to bring a next-generation supercomputer to the Oak Ridge National Laboratory (ORNL) in 2017. This new supercomputer, named Summit, will provide on science applications at least five times the performance of Titan, the OLCF's current hybrid CPU+GPU leadership system, and become the next peak in leadership-class computing systems for open science. In response to a call for proposals, the OLCF has selected and will be partnering with science and engineering application development teams for the porting and optimization of their applications and carrying out a science campaign at scale on Summit.
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### Speaker Organization
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National Center for Computational Sciences Oak Ridge National Laboratory Oak Ridge, TN, USA
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### Presentation
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<iframe src="https://openpowerfoundation.org/wp-content/uploads/2015/04/20150318-GTC.pdf" width="100%" height="450" frameborder="0"></iframe>
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[Download Presentation](https://openpowerfoundation.org/wp-content/uploads/2015/04/20150318-GTC.pdf)
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Back to Summit Details
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---
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title: "eASIC Joins the OpenPOWER Foundation to Offer Custom-designed Accelerator Chips"
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date: "2016-05-04"
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categories:
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- "press-releases"
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- "blogs"
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---
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