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41 lines
2.0 KiB
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41 lines
2.0 KiB
Markdown
---
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title: PSL / AFU Interface Specification
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group: accelerator
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publicreview: false
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tags:
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- powerservicelayer
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- psl
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- acceleratorfunctionalunit
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- afu
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- accelerator
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- capi1
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- capi2
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- pcie4
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- power8
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- power9
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date: 2016-03-15
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draft: false
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---
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A CAPI based accelerator interfaces to the POWER system through a logic unit called the Power Service Layer (PSL).
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The Accelerator Function Unit (AFU) contains the logic that implements the unique acceleration function.
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The POWER Service Layer to Accelerator Functional Unit (PSL / AFU) interface communicates to the acceleration logic running on the FPGA.
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Through this interface, the PSL offers services to the AFU.
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The services offered are cache-line oriented and allow the AFU to make buffering versus throughput trade-offs.
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The interface to the AFU is composed of six independent interfaces :
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- AFU Command Interface is the interface through which the AFU sends service requests to the PSL.
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- AFU Buffer Interface is the interface through which the PSL moves data to and from the AFU.
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- PSL Response Interface is the interface through which the PSL reports status about service requests.
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- AFU MMIO Interface is the interface through which software reads and writes can access registers within the AFU.
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- AFU Control Interface allows the PSL job management functions to control the state of the AFU.
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- AFU DMA Interface allows the AFU to send native PCIe Writes and Reads and to receive Read Completion data.
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Together these interfaces allow software to control the AFU state and allow the AFU to access data in the system.
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This document is a Standard Track, Work Group Specification work product owned by the Accelerator Workgroup and
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handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
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It was created using the Master Template Guide version 1.0.0.
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Comments, questions, etc. can be submitted to the public mailing list for this document at <aclwg-afu_psl@mailinglist.openpowerfoundation.org>.
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