You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Benjamin Herrenschmidt ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs ... This adds a simple bus that can be mastered from an external system via JTAG, which will be used to hookup various debug modules. It's loosely based on the RiscV model (hence the DMI name). The module currently only supports hooking up to a Xilinx BSCANE2 but it shouldn't be too hard to adapt it to support different TAPs if necessary. The JTAG protocol proper is not exactly the RiscV one at this point, though I might still change it. This comes with some sim variants of Xilinx BSCANE2 and BUFG and a test bench. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
..
dependencies.py	Initial import of microwatt	5 years ago
hash.py	Initial import of microwatt	5 years ago
mw_debug.py	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs	5 years ago
run_test.sh	Initial import of microwatt	5 years ago
test_micropython.py	Initial import of microwatt	5 years ago
test_micropython_long.py	Initial import of microwatt	5 years ago
verific.sh	Fix verific script with new VHDL files	5 years ago