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ee52fd4d80
This adds a simple bus that can be mastered from an external system via JTAG, which will be used to hookup various debug modules. It's loosely based on the RiscV model (hence the DMI name). The module currently only supports hooking up to a Xilinx BSCANE2 but it shouldn't be too hard to adapt it to support different TAPs if necessary. The JTAG protocol proper is not exactly the RiscV one at this point, though I might still change it. This comes with some sim variants of Xilinx BSCANE2 and BUFG and a test bench. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| fpga | ||
| hello_world | ||
| scripts | 5 years ago | |
| sim-unisim | 5 years ago | |
| tests | ||
| .gitignore | ||
| .travis.yml | ||
| LICENSE | ||
| Makefile | 5 years ago | |
| README.md | ||
| common.vhdl | ||
| core.vhdl | ||
| core_tb.vhdl | ||
| cr_file.vhdl | ||
| crhelpers.vhdl | 5 years ago | |
| decode1.vhdl | ||
| decode2.vhdl | ||
| decode_types.vhdl | ||
| dmi_dtm_dummy.vhdl | 5 years ago | |
| dmi_dtm_tb.vhdl | 5 years ago | |
| dmi_dtm_xilinx.vhdl | 5 years ago | |
| execute1.vhdl | ||
| execute2.vhdl | ||
| fetch1.vhdl | ||
| fetch2.vhdl | ||
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| helpers.vhdl | 5 years ago | |
| icache.vhdl | ||
| icache_tb.vhdl | ||
| insn_helpers.vhdl | 5 years ago | |
| loadstore1.vhdl | ||
| loadstore2.vhdl | ||
| microwatt.core | 5 years ago | |
| multiply.vhdl | ||
| multiply_tb.vhdl | ||
| ppc_fx_insns.vhdl | ||
| register_file.vhdl | ||
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_uart.vhdl | ||
| simple_ram_behavioural.vhdl | ||
| simple_ram_behavioural_helpers.vhdl | ||
| simple_ram_behavioural_helpers_c.c | ||
| simple_ram_behavioural_tb.bin | ||
| simple_ram_behavioural_tb.vhdl | ||
| soc.vhdl | 5 years ago | |
| wishbone_arbiter.vhdl | 5 years ago | |
| wishbone_types.vhdl | ||
| writeback.vhdl | ||
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
- Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- Need to implement a simple non pipelined divide
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)