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Paul Mackerras
d458b5845c
At present, code (such as simple_random) which produces serial port output during the first few milliseconds of operation produces garbled output. The reason is that the clock has not yet stabilized and is running slow, resulting in the bit time of the serial characters being too long. The ECP5 data sheet says that the phase detector should be operated between 10 and 400 MHz. The current code operates it at 2MHz. Consequently, the PLL lock indication doesn't work, i.e. it is always zero. The current code works around that by inverting it, i.e. taking the "not locked" indication to mean "locked". Instead, we now run it at 12MHz, chosen because the common external clock inputs on ECP5 boards are 12MHz and 48MHz. Normally this would mean that the available system clock frequencies would be multiples of 12MHz, but this is a little inconvenient as we use 40MHz on the Orange Crab v0.21 boards. Instead, by using the secondary clock output for feedback, we can have any divisor of the PLL frequency as the system clock frequency. The ECP5 data sheet says the PLL oscillator can run at 400 to 800 MHz. Here we choose 480MHz since that allows us to generate 40MHz and 48MHz easily and is a multiple of 12MHz. With this, the lock signal works correctly, and the inversion can be removed. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
3 years ago | |
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| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | ||
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | ||
| top-arty.vhdl | ||
| top-generic.vhdl | ||
| top-genesys2.vhdl | ||
| top-nexys-video.vhdl | ||
| top-wukong-v2.vhdl | ||
| wukong-v2.xdc | ||