fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz

50Mhz clkin, 100Mhz sys_clk, as needed for Wukon v2

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

fpga/clk_gen_plle2.vhd

@@ -70,6 +70,18 @@ architecture rtl of clock_generator is
                 report "Unsupported output frequency" severity failure;
                 return bad_settings;
             end case;
+        when 50000000 =>
+            case output_hz is
+            when 100000000 =>
+                return (clkin_period  => 20.0,
+                        clkfbout_mult => 32,
+                        clkout_divide => 16,
+                        divclk_divide => 1,
+                        force_rst     => '0');
+            when others =>
+                report "Unsupported output frequency" severity failure;
+                return bad_settings;
+            end case;
         when others =>
             report "Unsupported input frequency" severity failure;
             return bad_settings;