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microwatt/litedram/extras
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Benjamin Herrenschmidt 6828e93113 litedram: Test bench 
The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.

Includes a litedram update to be able to operate the sim model without
inits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
VexRiscv.v litedram: Add basic support for LiteX LiteDRAM 5 years ago
fusesoc-add-files.py litedram: Add support for booting without BRAM 5 years ago
sim_dram_verilate.mk litedram: Add simulation support 5 years ago
sim_litedram.vhdl litedram: Add simulation support 5 years ago
sim_litedram_c.cpp litedram: Add simulation support 5 years ago
wave.gtkw litedram: Add an L2 cache with store queue 5 years ago
wave.opt litedram: Add an L2 cache with store queue 5 years ago
wave_tb.gtkw litedram: Test bench 5 years ago
wrapper-mw-init.vhdl litedram: Add an L2 cache with store queue 5 years ago
wrapper-self-init.vhdl litedram: Add simulation support 5 years ago