microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Anton Blanchard 467630573c Dump CTR, LR and CR on sim termination, and update our tests Right now our test cases fold the SPRs into the GPRs. That makes debugging fails more difficult than it needs to be, so print out the CTR, LR and CR. We still need to print the XER, but that is in two spots in microwatt and will take some more work. This also adds many instructions to the tests that we have added lately including overflow instructions, CR logicals and mt/mfxer. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		5 years ago
fpga	Add SPI configuration to Xilinx constraint files	5 years ago
hello_world	…
media	…
scripts	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
sim-unisim	…
tests	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	sprs: Store common SPRs in register file	5 years ago
README.md	Point to upstream micropython	5 years ago
cache_ram.vhdl	…
common.vhdl	sprs: Store common SPRs in register file	5 years ago
control.vhdl	control: Fix build issue with Fedora 31 version of GHDL	5 years ago
core.vhdl	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
core_debug.vhdl	…
core_tb.vhdl	…
countzero.vhdl	…
countzero_tb.vhdl	…
cr_file.vhdl	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
cr_hazard.vhdl	sprs: Store common SPRs in register file	5 years ago
crhelpers.vhdl	…
dcache.vhdl	Add basic XER support	5 years ago
dcache_tb.vhdl	…
decode1.vhdl	Implement CRNOR and friends	5 years ago
decode2.vhdl	decode2: Minor cleanup	5 years ago
decode_types.vhdl	sprs: Store common SPRs in register file	5 years ago
divider.vhdl	divider: Fix overflow calculation	5 years ago
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	Implement CRNOR and friends	5 years ago
fetch1.vhdl	…
fetch2.vhdl	…
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	sprs: Store common SPRs in register file	5 years ago
helpers.vhdl	execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions	5 years ago
icache.vhdl	…
icache_tb.vhdl	…
icache_test.bin	…
insn_helpers.vhdl	Implement CRNOR and friends	5 years ago
loadstore1.vhdl	Add basic XER support	5 years ago
logical.vhdl	…
microwatt.core	…
multiply.vhdl	Add basic XER support	5 years ago
multiply_tb.vhdl	…
plru.vhdl	…
plru_tb.vhdl	…
ppc_fx_insns.vhdl	sprs: Store common SPRs in register file	5 years ago
register_file.vhdl	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
rotator.vhdl	…
rotator_tb.vhdl	…
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_uart.vhdl	…
soc.vhdl	…
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	…
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	sprs: Store common SPRs in register file	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)