Benjamin Herrenschmidt 025cf5efe8 syscon: Add syscon registers ... These provides some info about the SoC (though it's still somewhat incomplete and needs more work, see comments). There's also a control register for selecting DRAM vs. BRAM at 0 (and for soft-resetting the SoC but that isn't wired up yet). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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sdram_init	syscon: Add syscon registers	5 years ago
arty.yml	litedram: Add basic support for LiteX LiteDRAM	5 years ago
generate.py	litedram: Add basic support for LiteX LiteDRAM	5 years ago
nexys-video.yml	litedram: Add basic support for LiteX LiteDRAM	5 years ago
wrapper-mw-init.vhdl	litedram: Add basic support for LiteX LiteDRAM	5 years ago
wrapper-self-init.vhdl	litedram: Add basic support for LiteX LiteDRAM	5 years ago