23 changed files with 205 additions and 329 deletions
--- a/README.md
+++ b/README.md
@ -103,8 +103,14 @@ sudo dnf install fusesoc
 ```
 fusesoc init
-fusesoc fetch uart16550
+```
-fusesoc library add microwatt /path/to/microwatt
+
 - Create a working directory and point FuseSoC at microwatt:
 ```
 mkdir microwatt-fusesoc
 cd microwatt-fusesoc
 fusesoc library add microwatt /path/to/microwatt/
 ```
 - Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
@ -122,68 +128,6 @@ You should then be able to see output via the serial port of the board (/dev/tty
 fusesoc run --target=nexys_video microwatt
 ```
 ## Linux on Microwatt
 Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested
 platform, but it's also been tested on the OrangeCrab and ButterStick.
 1. Use buildroot to create a userspace
   A small change is required to glibc in order to support the VMX/AltiVec-less
   Microwatt, as float128 support is mandiatory and for this in GCC requires
   VSX/AltiVec. This change is included in Joel's buildroot fork, along with a
   defconfig:
   ```
   git clone -b microwatt https://github.com/shenki/buildroot
   cd buildroot
   make ppc64le_microwatt_defconfig
   make
   ```
   The output is `output/images/rootfs.cpio`.
 2. Build the Linux kernel
   ```
   git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
   cd linux
   make ARCH=powerpc microwatt_defconfig
   make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
     CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`
   ```
   The output is `arch/powerpc/boot/dtbImage.microwatt.elf`.
 3. Build gateware using FuseSoC
   First configure FuseSoC as above.
   ```
   fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0
   ```
   The output is `build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit`.
 4. Program the flash
   This operation will overwrite the contents of your flash.
   For the Arty A7 A100, set `FLASH_ADDRESS` to `0x400000` and pass `-f a100`.
   For the Arty A7 A35, set `FLASH_ADDRESS` to `0x300000` and pass `-f a35`.
   ```
   microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
   microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS
   ```
 5. Connect to the second USB TTY device exposed by the FPGA
   ```
   minicom -D /dev/ttyUSB1
   ```
   The gateware has firmware that will look at `FLASH_ADDRESS` and attempt to
   parse an ELF there, loading it to the address specified in the ELF header
   and jumping to it.
 ## Testing
 - A simple test suite containing random execution test cases and a couple of
--- a/common.vhdl
+++ b/common.vhdl
@ -200,6 +200,7 @@ package common is
        priv_mode : std_ulogic;
        big_endian : std_ulogic;
 	stop_mark: std_ulogic;
        sequential: std_ulogic;
        predicted : std_ulogic;
        pred_ntaken : std_ulogic;
 	nia: std_ulogic_vector(63 downto 0);
--- a/control.vhdl
+++ b/control.vhdl
@ -64,8 +64,8 @@ architecture rtl of control is
    signal r_int, rin_int : reg_internal_type := reg_internal_init;
-    signal gpr_write_valid : std_ulogic;
+    signal gpr_write_valid : std_ulogic := '0';
-    signal cr_write_valid  : std_ulogic;
+    signal cr_write_valid  : std_ulogic := '0';
    type tag_register is record
        wr_gpr : std_ulogic;
@ -245,8 +245,6 @@ begin
        end if;
        if rst = '1' then
            gpr_write_valid <= '0';
            cr_write_valid <= '0';
            v_int := reg_internal_init;
            valid_tmp := '0';
        end if;
--- a/core.vhdl
+++ b/core.vhdl
@ -117,20 +117,21 @@ architecture behave of core is
    signal complete: instr_tag_t;
    signal terminate: std_ulogic;
    signal core_rst: std_ulogic;
    signal icache_inv: std_ulogic;
    signal do_interrupt: std_ulogic;
    -- Delayed/Latched resets and alt_reset
-    signal rst_fetch1  : std_ulogic;
+    signal rst_fetch1  : std_ulogic := '1';
-    signal rst_fetch2  : std_ulogic;
+    signal rst_fetch2  : std_ulogic := '1';
-    signal rst_icache  : std_ulogic;
+    signal rst_icache  : std_ulogic := '1';
-    signal rst_dcache  : std_ulogic;
+    signal rst_dcache  : std_ulogic := '1';
-    signal rst_dec1    : std_ulogic;
+    signal rst_dec1    : std_ulogic := '1';
-    signal rst_dec2    : std_ulogic;
+    signal rst_dec2    : std_ulogic := '1';
-    signal rst_ex1     : std_ulogic;
+    signal rst_ex1     : std_ulogic := '1';
-    signal rst_fpu     : std_ulogic;
+    signal rst_fpu     : std_ulogic := '1';
-    signal rst_ls1     : std_ulogic;
+    signal rst_ls1     : std_ulogic := '1';
-    signal rst_wback   : std_ulogic;
+    signal rst_wback   : std_ulogic := '1';
-    signal rst_dbg     : std_ulogic;
+    signal rst_dbg     : std_ulogic := '1';
    signal alt_reset_d : std_ulogic;
    signal sim_cr_dump: std_ulogic;
--- a/core_debug.vhdl
+++ b/core_debug.vhdl
@ -154,7 +154,6 @@ begin
                stopping <= '0';
                terminated <= '0';
                log_trigger_delay <= 0;
                gspr_index <= (others => '0');
            else
                if do_log_trigger = '1' or log_trigger_delay /= 0 then
                    if log_trigger_delay = 255 then
--- a/dcache.vhdl
+++ b/dcache.vhdl
@ -1121,6 +1121,7 @@ begin
    rams: for i in 0 to NUM_WAYS-1 generate
 	signal do_read  : std_ulogic;
 	signal rd_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
 	signal do_write : std_ulogic;
 	signal wr_addr  : std_ulogic_vector(ROW_BITS-1 downto 0);
 	signal wr_data  : std_ulogic_vector(wishbone_data_bits-1 downto 0);
 	signal wr_sel   : std_ulogic_vector(ROW_SIZE-1 downto 0);
--- a/divider.vhdl
+++ b/divider.vhdl
@ -42,8 +42,6 @@ begin
                quot <= (others => '0');
                running <= '0';
                count <= "0000000";
                is_32bit <= '0';
                overflow <= '0';
            elsif d_in.valid = '1' then
                if d_in.is_extended = '1'  then
                    dend <= '0' & d_in.dividend & x"0000000000000000";
--- a/execute1.vhdl
+++ b/execute1.vhdl
@ -99,8 +99,8 @@ architecture behaviour of execute1 is
    signal mshort_p : std_ulogic_vector(31 downto 0) := (others => '0');
    signal valid_in : std_ulogic;
-    signal ctrl: ctrl_t;
+    signal ctrl: ctrl_t := (others => (others => '0'));
-    signal ctrl_tmp: ctrl_t;
+    signal ctrl_tmp: ctrl_t := (others => (others => '0'));
    signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
    signal rot_sign_ext: std_ulogic;
    signal rotator_result: std_ulogic_vector(63 downto 0);
@ -113,6 +113,8 @@ architecture behaviour of execute1 is
    signal misc_result: std_ulogic_vector(63 downto 0);
    signal muldiv_result: std_ulogic_vector(63 downto 0);
    signal spr_result: std_ulogic_vector(63 downto 0);
    signal result_mux_sel: std_ulogic_vector(2 downto 0);
    signal sub_mux_sel: std_ulogic_vector(2 downto 0);
    signal next_nia : std_ulogic_vector(63 downto 0);
    signal current: Decode2ToExecute1Type;
@ -404,7 +406,6 @@ begin
                r <= reg_type_init;
                ctrl.tb <= (others => '0');
                ctrl.dec <= (others => '0');
                ctrl.cfar <= (others => '0');
                ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
            else
                r <= rin;
--- a/fpu.vhdl
+++ b/fpu.vhdl
@ -16,7 +16,7 @@ entity fpu is
        clk : in std_ulogic;
        rst : in std_ulogic;
-        e_in  : in  Execute1ToFPUType;
+        e_in  : in  Execute1toFPUType;
        e_out : out FPUToExecute1Type;
        w_out : out FPUToWritebackType
@ -549,10 +549,6 @@ begin
                r.do_intr <= '0';
                r.fpscr <= (others => '0');
                r.writing_back <= '0';
                r.dest_fpr <= (others =>'0');
                r.cr_mask <= (others =>'0');
                r.cr_result <= (others =>'0');
                r.instr_tag.valid <= '0';
            else
                assert not (r.state /= IDLE and e_in.valid = '1') severity failure;
                r <= rin;
--- a/gpio.vhdl
+++ b/gpio.vhdl
@ -40,8 +40,8 @@ architecture behaviour of gpio is
    constant GPIO_REG_DATA_CLR : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00101";
    -- Current output value and direction
-    signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
-    signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
    signal reg_in1  : std_ulogic_vector(NGPIO - 1 downto 0);
    signal reg_in2  : std_ulogic_vector(NGPIO - 1 downto 0);
--- a/hello_world/head.S
+++ b/hello_world/head.S
@ -60,25 +60,11 @@ _start:
 .global boot_entry
 boot_entry:
 	LOAD_IMM64(%r10,__bss_start)
 	LOAD_IMM64(%r11,__bss_end)
 	subf	%r11,%r10,%r11
 	addi	%r11,%r11,63
 	srdi.	%r11,%r11,6
 	beq	2f
 	mtctr	%r11
 1:	dcbz	0,%r10
 	addi	%r10,%r10,64
 	bdnz	1b
 	/* setup stack */
-2:	LOAD_IMM64(%r1,__stack_top)
+	LOAD_IMM64(%r1, STACK_TOP - 0x100)
 	li	%r0,0
 	stdu	%r0,-32(%r1)
 	LOAD_IMM64(%r12, main)
-	mtctr	%r12
+	mtctr	%r12,
 	bctrl
 	attn // terminate on exit
 	b .
 #define EXCEPTION(nr)		\
--- a/hello_world/hello_world.bin
+++ b/hello_world/hello_world.bin
--- a/hello_world/hello_world.elf
+++ b/hello_world/hello_world.elf
--- a/hello_world/hello_world.hex
+++ b/hello_world/hello_world.hex
@ -35,24 +35,24 @@ a64b5a7d14004a39
 a602487d05009f42
 a64b5a7d14004a39
 2402004ca64b7b7d
-3d40000048000004
+3c20000048000004
 794a07c6614a0000
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+0000000000000000
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+0000000000000000
 0000000000000000
 0000000000000000
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@ -510,150 +510,150 @@ f801ffe138000000
 0000000000000000
 0000000000000000
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 4bffffd060000000
 0100000000000000
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 7c0004ac39290014
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 4e8000205463063e
 39290010e92a0000
 7d204eea7c0004ac
 4082ffec71290001
 38630008e86a0000
 7c601eea7c0004ac
 000000004bffffd0
-0000018001000000
+0000000000000000
 384298003c400001
-8922810860000000
+8922809060000000
-3942810060000000
+3942808860000000
-418200302c090000
+4182002c2c090000
 39290014e92a0000
 7d204eaa7c0004ac
-4182ffec71290001
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-7c0004ac38630008
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 0000000000000000
 3c40000100000000
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-3c40000100000000
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--- a/hello_world/powerpc.lds
+++ b/hello_world/powerpc.lds
@ -1,27 +1,13 @@
 SECTIONS
 {
 	. = 0;
 	_start = .;
 	. = 0;
 	.head : {
 		KEEP(*(.head))
 	}
 	. = 0x1000;
-	.text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
+	.text : { *(.text) }
 	. = 0x1800;
-	.data : { *(.data) *(.data.*) *(.got) *(.toc) }
+	.data : { *(.data) }
-	. = ALIGN(0x80);
+	.bss : { *(.bss) }
 	__bss_start = .;
 	.bss : {
 		*(.dynsbss)
 		*(.sbss)
 		*(.scommon)
 		*(.dynbss)
 		*(.bss)
 		*(.common)
 		*(.bss.*)
 	}
 	. = ALIGN(0x80);
 	__bss_end = .;
 	. = . + 0x2000;
 	__stack_top = .;
 }
--- a/icache.vhdl
+++ b/icache.vhdl
@ -555,11 +555,7 @@ begin
 	--       I prefer not to do just yet as it would force fetch2 to know about
 	--       some of the cache geometry information.
 	--
 	if r.hit_valid = '1' then
        i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
 	else
            i_out.insn <= (others => '0');
 	end if;
 	i_out.valid <= r.hit_valid;
 	i_out.nia <= r.hit_nia;
 	i_out.stop_mark <= r.hit_smark;
@ -824,7 +820,4 @@ begin
        end process;
        log_out <= log_data;
    end generate;
    events <= ev;
 end;
--- a/icache_tb.vhdl
+++ b/icache_tb.vhdl
@ -74,9 +74,6 @@ begin
        i_out.req <= '0';
        i_out.nia <= (others => '0');
        i_out.stop_mark <= '0';
        i_out.priv_mode <= '1';
        i_out.virt_mode <= '0';
        i_out.big_endian <= '0';
        m_out.tlbld <= '0';
        m_out.tlbie <= '0';
--- a/loadstore1.vhdl
+++ b/loadstore1.vhdl
@ -275,27 +275,10 @@ begin
        if rising_edge(clk) then
            if rst = '1' then
                r1.req.valid <= '0';
                r1.req.tlbie <= '0';
                r1.req.is_slbia <= '0';
                r1.req.instr_fault <= '0';
                r1.req.load <= '0';
                r1.req.priv_mode <= '0';
                r1.req.sprn <= (others => '0');
                r1.req.xerc <= xerc_init;
                r2.req.valid <= '0';
                r2.req.tlbie <= '0';
                r2.req.is_slbia <= '0';
                r2.req.instr_fault <= '0';
                r2.req.load <= '0';
                r2.req.priv_mode <= '0';
                r2.req.sprn <= (others => '0');
                r2.req.xerc <= xerc_init;
                r2.wait_dc <= '0';
                r2.wait_mmu <= '0';
                r2.one_cycle <= '0';
                r3.dar <= (others => '0');
                r3.dsisr <= (others => '0');
                r3.state <= IDLE;
@ -303,8 +286,6 @@ begin
                r3.interrupt <= '0';
                r3.stage1_en <= '1';
                r3.convert_lfs <= '0';
                r3.events.load_complete <= '0';
                r3.events.store_complete <= '0';
                flushing <= '0';
            else
                r1 <= r1in;
--- a/soc.vhdl
+++ b/soc.vhdl
@ -61,7 +61,6 @@ entity soc is
        HAS_BTC            : boolean := true;
        HAS_SHORT_MULT     : boolean := false;
 	DISABLE_FLATTEN_CORE : boolean := false;
        ALT_RESET_ADDRESS  : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1');
 	HAS_DRAM           : boolean  := false;
 	DRAM_SIZE          : integer := 0;
        DRAM_INIT_SIZE     : integer := 0;
@ -223,15 +222,15 @@ architecture behaviour of soc is
    signal dmi_core_ack   : std_ulogic;
    -- Delayed/latched resets and alt_reset
-    signal rst_core    : std_ulogic;
+    signal rst_core    : std_ulogic := '1';
-    signal rst_uart    : std_ulogic;
+    signal rst_uart    : std_ulogic := '1';
-    signal rst_xics    : std_ulogic;
+    signal rst_xics    : std_ulogic := '1';
-    signal rst_spi     : std_ulogic;
+    signal rst_spi     : std_ulogic := '1';
-    signal rst_gpio    : std_ulogic;
+    signal rst_gpio    : std_ulogic := '1';
-    signal rst_bram    : std_ulogic;
+    signal rst_bram    : std_ulogic := '1';
-    signal rst_dtm     : std_ulogic;
+    signal rst_dtm     : std_ulogic := '1';
-    signal rst_wbar    : std_ulogic;
+    signal rst_wbar    : std_ulogic := '1';
-    signal rst_wbdb    : std_ulogic;
+    signal rst_wbdb    : std_ulogic := '1';
    signal alt_reset_d : std_ulogic;
    -- IO branch split:
@ -337,7 +336,7 @@ begin
            HAS_BTC => HAS_BTC,
            HAS_SHORT_MULT => HAS_SHORT_MULT,
 	    DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
-	    ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
+	    ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
            LOG_LENGTH => LOG_LENGTH,
            ICACHE_NUM_LINES => ICACHE_NUM_LINES,
            ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
--- a/spi_flash_ctrl.vhdl
+++ b/spi_flash_ctrl.vhdl
@ -50,7 +50,7 @@ architecture rtl of spi_flash_ctrl is
    constant SPI_REG_INVALID      : std_ulogic_vector(SPI_REG_BITS-1 downto 0) := "111";
    -- Control register
-    signal ctrl_reg    : std_ulogic_vector(15 downto 0);
+    signal ctrl_reg    : std_ulogic_vector(15 downto 0) := (others => '0');
    alias  ctrl_reset  : std_ulogic is ctrl_reg(0);
    alias  ctrl_cs     : std_ulogic is ctrl_reg(1);
    alias  ctrl_rsrv1  : std_ulogic is ctrl_reg(2);
@ -58,7 +58,7 @@ architecture rtl of spi_flash_ctrl is
    alias  ctrl_div    : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);
    -- Auto mode config register
-    signal auto_cfg_reg     : std_ulogic_vector(29 downto 0);
+    signal auto_cfg_reg     : std_ulogic_vector(29 downto 0) := (others => '0');
    alias  auto_cfg_cmd     : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
    alias  auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
    alias  auto_cfg_mode    : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
@ -126,9 +126,9 @@ architecture rtl of spi_flash_ctrl is
    signal auto_latch_adr : std_ulogic;
    -- Automatic mode latches
-    signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0);
+    signal auto_data      : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0');
-    signal auto_cnt       : integer range 0 to 63;
+    signal auto_cnt       : integer range 0 to 63 := 0;
-    signal auto_state     : auto_state_t;
+    signal auto_state     : auto_state_t := AUTO_BOOT;
    signal auto_last_addr : std_ulogic_vector(31 downto 0);
 begin
@ -351,8 +351,6 @@ begin
            if rst = '1' then
                auto_last_addr <= (others => '0');
                auto_state <= AUTO_BOOT;
                auto_cnt <= 0;
                auto_data  <= (others => '0');
            else
                auto_state <= auto_next;
                auto_cnt   <= auto_cnt_next;
--- a/spi_rxtx.vhdl
+++ b/spi_rxtx.vhdl
@ -126,10 +126,10 @@ architecture rtl of spi_rxtx is
    signal dat_ack_l : std_ulogic;
    -- Delayed recv signal for the read machine
-    signal sck_recv_d : std_ulogic;
+    signal sck_recv_d : std_ulogic := '0';
    -- Input shift register (use fifo ?)
-    signal ireg       : std_ulogic_vector(7 downto 0);
+    signal ireg       : std_ulogic_vector(7 downto 0) := (others => '0');
    -- Bit counter
    signal bit_count  : std_ulogic_vector(2 downto 0);
@ -157,7 +157,7 @@ architecture rtl of spi_rxtx is
    end;
    type state_t is (STANDBY, DATA);
-    signal state : state_t;
+    signal state : state_t := STANDBY;
 begin
    -- We don't support multiple data lines at this point
@ -349,9 +349,6 @@ begin
    shift_in: process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                ireg <= (others => '0');
            end if;
            -- Delay the receive signal to match the input latch
            if state = DATA then
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;
 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
    -- RAM interface
    signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
--- a/xics.vhdl
+++ b/xics.vhdl
@ -269,7 +269,7 @@ architecture rtl of xics_ics is
    begin
        masked := x"00";
        masked(PRIO_BITS - 1 downto 0) := (others => '1');
-        if unsigned(pri8) >= unsigned(masked) then
+        if pri8 >= masked then
            return pri_masked;
        else
            return pri8(PRIO_BITS-1 downto 0);