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remove-pot
| Author | SHA1 | Date |
|---|---|---|
Anton Blanchard
|
1d29cdcfb4 | 3 years ago |
@ -1,91 +0,0 @@
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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--! @brief A generic FIFO module.
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--! Adopted from the FIFO module in <https://github.com/skordal/smallthings>.
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entity pp_fifo is
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generic(
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DEPTH : natural := 64;
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WIDTH : natural := 32
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);
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port(
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-- Control lines:
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clk : in std_logic;
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reset : in std_logic;
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-- Status lines:
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full : out std_logic;
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empty : out std_logic;
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-- Data in:
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data_in : in std_logic_vector(WIDTH - 1 downto 0);
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data_out : out std_logic_vector(WIDTH - 1 downto 0);
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push, pop : in std_logic
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);
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end entity pp_fifo;
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architecture behaviour of pp_fifo is
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type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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signal memory : memory_array := (others => (others => '0'));
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subtype index_type is integer range 0 to DEPTH - 1;
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signal top, bottom : index_type;
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type fifo_op is (FIFO_POP, FIFO_PUSH);
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signal prev_op : fifo_op := FIFO_POP;
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begin
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empty <= '1' when top = bottom and prev_op = FIFO_POP else '0';
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full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0';
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read: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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bottom <= 0;
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else
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if pop = '1' then
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data_out <= memory(bottom);
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bottom <= (bottom + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process read;
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write: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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top <= 0;
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else
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if push = '1' then
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memory(top) <= data_in;
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top <= (top + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process write;
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set_prev_op: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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prev_op <= FIFO_POP;
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else
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if push = '1' and pop = '1' then
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-- Keep the same value for prev_op
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elsif push = '1' then
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prev_op <= FIFO_PUSH;
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elsif pop = '1' then
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prev_op <= FIFO_POP;
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end if;
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end if;
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end if;
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end process set_prev_op;
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end architecture behaviour;
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@ -1,395 +0,0 @@
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2016 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--! @brief Simple UART module.
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--! The following registers are defined:
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--! |--------------------|--------------------------------------------|
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--! | Address | Description |
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--! |--------------------|--------------------------------------------|
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--! | 0x00 | Transmit register (write-only) |
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--! | 0x08 | Receive register (read-only) |
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--! | 0x10 | Status register (read-only) |
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--! | 0x18 | Sample clock divisor register (read/write) |
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--! | 0x20 | Interrupt enable register (read/write) |
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--! |--------------------|--------------------------------------------|
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--!
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--! The status register contains the following bits:
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--! - Bit 0: receive buffer empty
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--! - Bit 1: transmit buffer empty
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--! - Bit 2: receive buffer full
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--! - Bit 3: transmit buffer full
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--!
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--! The sample clock divisor should be set according to the formula:
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--! sample_clk = (f_clk / (baudrate * 16)) - 1
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--!
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--! If the sample clock divisor register is set to 0, the sample clock
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--! is stopped.
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--!
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--! Interrupts are enabled by setting the corresponding bit in the interrupt
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--! enable register. The following bits are available:
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--! - Bit 0: data received (receive buffer not empty)
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--! - Bit 1: ready to send data (transmit buffer empty)
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entity pp_soc_uart is
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generic(
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FIFO_DEPTH : natural := 64 --! Depth of the input and output FIFOs.
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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-- UART ports:
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txd : out std_logic;
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rxd : in std_logic;
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-- Interrupt signal:
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irq : out std_logic;
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-- Wishbone ports:
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wb_adr_in : in std_logic_vector(11 downto 0);
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wb_dat_in : in std_logic_vector( 7 downto 0);
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wb_dat_out : out std_logic_vector( 7 downto 0);
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wb_we_in : in std_logic;
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wb_cyc_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_ack_out : out std_logic
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);
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end entity pp_soc_uart;
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architecture behaviour of pp_soc_uart is
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subtype bitnumber is natural range 0 to 7; --! Type representing the index of a bit.
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-- UART sample clock signals:
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signal sample_clk : std_logic;
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signal sample_clk_divisor : std_logic_vector(7 downto 0);
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signal sample_clk_counter : std_logic_vector(sample_clk_divisor'range);
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-- UART receive process signals:
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type rx_state_type is (IDLE, RECEIVE, STARTBIT, STOPBIT);
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signal rx_state : rx_state_type;
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signal rx_byte : std_logic_vector(7 downto 0);
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signal rx_current_bit : bitnumber;
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subtype rx_sample_counter_type is natural range 0 to 15;
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signal rx_sample_counter : rx_sample_counter_type;
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signal rx_sample_value : rx_sample_counter_type;
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subtype rx_sample_delay_type is natural range 0 to 7;
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signal rx_sample_delay : rx_sample_delay_type;
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-- UART transmit process signals:
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type tx_state_type is (IDLE, TRANSMIT, STOPBIT);
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signal tx_state : tx_state_type;
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signal tx_byte : std_logic_vector(7 downto 0);
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signal tx_current_bit : bitnumber;
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-- UART transmit clock:
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subtype uart_tx_counter_type is natural range 0 to 15;
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signal uart_tx_counter : uart_tx_counter_type := 0;
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signal uart_tx_clk : std_logic;
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-- Buffer signals:
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signal send_buffer_full, send_buffer_empty : std_logic;
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signal recv_buffer_full, recv_buffer_empty : std_logic;
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signal send_buffer_input, send_buffer_output : std_logic_vector(7 downto 0);
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signal recv_buffer_input, recv_buffer_output : std_logic_vector(7 downto 0);
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signal send_buffer_push, send_buffer_pop : std_logic := '0';
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signal recv_buffer_push, recv_buffer_pop : std_logic := '0';
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-- IRQ enable signals:
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signal irq_recv_enable, irq_tx_ready_enable : std_logic := '0';
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-- Wishbone signals:
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type wb_state_type is (IDLE, WRITE_ACK, READ_ACK);
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signal wb_state : wb_state_type;
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signal rxd2 : std_logic := '1';
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signal rxd3 : std_logic := '1';
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signal txd2 : std_ulogic := '1';
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begin
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irq <= (irq_recv_enable and (not recv_buffer_empty))
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or (irq_tx_ready_enable and send_buffer_empty);
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---------- UART receive ----------
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recv_buffer_input <= rx_byte;
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-- Add a few FFs on the RX input to avoid metastability issues
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process (clk) is
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begin
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if rising_edge(clk) then
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rxd3 <= rxd2;
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rxd2 <= rxd;
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end if;
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end process;
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txd <= txd2;
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uart_receive: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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rx_state <= IDLE;
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recv_buffer_push <= '0';
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else
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case rx_state is
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when IDLE =>
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if recv_buffer_push = '1' then
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recv_buffer_push <= '0';
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end if;
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if sample_clk = '1' and rxd3 = '0' then
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rx_sample_value <= rx_sample_counter;
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rx_sample_delay <= 0;
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rx_current_bit <= 0;
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rx_state <= STARTBIT;
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end if;
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when STARTBIT =>
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if sample_clk = '1' then
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if rx_sample_delay = 7 then
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rx_state <= RECEIVE;
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rx_sample_value <= rx_sample_counter;
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rx_sample_delay <= 0;
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else
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rx_sample_delay <= rx_sample_delay + 1;
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end if;
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end if;
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when RECEIVE =>
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if sample_clk = '1' and rx_sample_counter = rx_sample_value then
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if rx_current_bit /= 7 then
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rx_byte(rx_current_bit) <= rxd3;
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rx_current_bit <= rx_current_bit + 1;
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else
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rx_byte(rx_current_bit) <= rxd3;
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rx_state <= STOPBIT;
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end if;
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end if;
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when STOPBIT =>
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if sample_clk = '1' and rx_sample_counter = rx_sample_value then
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rx_state <= IDLE;
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if recv_buffer_full = '0' then
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recv_buffer_push <= '1';
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end if;
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end if;
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end case;
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end if;
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end if;
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end process uart_receive;
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sample_counter: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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rx_sample_counter <= 0;
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elsif sample_clk = '1' then
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if rx_sample_counter = 15 then
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rx_sample_counter <= 0;
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else
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rx_sample_counter <= rx_sample_counter + 1;
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end if;
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end if;
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end if;
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end process sample_counter;
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---------- UART transmit ----------
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tx_byte <= send_buffer_output;
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uart_transmit: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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txd2 <= '1';
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tx_state <= IDLE;
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send_buffer_pop <= '0';
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tx_current_bit <= 0;
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else
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case tx_state is
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when IDLE =>
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if send_buffer_empty = '0' and uart_tx_clk = '1' then
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txd2 <= '0';
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send_buffer_pop <= '1';
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tx_current_bit <= 0;
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tx_state <= TRANSMIT;
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elsif uart_tx_clk = '1' then
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txd2 <= '1';
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end if;
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when TRANSMIT =>
|
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if send_buffer_pop = '1' then
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send_buffer_pop <= '0';
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elsif uart_tx_clk = '1' and tx_current_bit = 7 then
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txd2 <= tx_byte(tx_current_bit);
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tx_state <= STOPBIT;
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elsif uart_tx_clk = '1' then
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txd2 <= tx_byte(tx_current_bit);
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tx_current_bit <= tx_current_bit + 1;
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end if;
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when STOPBIT =>
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if uart_tx_clk = '1' then
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txd2 <= '1';
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tx_state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process uart_transmit;
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|
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uart_tx_clock_generator: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
|
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uart_tx_counter <= 0;
|
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uart_tx_clk <= '0';
|
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else
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if sample_clk = '1' then
|
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if uart_tx_counter = 15 then
|
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uart_tx_counter <= 0;
|
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uart_tx_clk <= '1';
|
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else
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uart_tx_counter <= uart_tx_counter + 1;
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uart_tx_clk <= '0';
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end if;
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else
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uart_tx_clk <= '0';
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end if;
|
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end if;
|
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end if;
|
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end process uart_tx_clock_generator;
|
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|
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---------- Sample clock generator ----------
|
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|
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sample_clock_generator: process(clk)
|
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begin
|
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if rising_edge(clk) then
|
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if reset = '1' then
|
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sample_clk_counter <= (others => '0');
|
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sample_clk <= '0';
|
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else
|
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if sample_clk_divisor /= x"00" then
|
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if sample_clk_counter = sample_clk_divisor then
|
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sample_clk_counter <= (others => '0');
|
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sample_clk <= '1';
|
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else
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sample_clk_counter <= std_logic_vector(unsigned(sample_clk_counter) + 1);
|
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sample_clk <= '0';
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end if;
|
||||
end if;
|
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end if;
|
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end if;
|
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end process sample_clock_generator;
|
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|
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---------- Data Buffers ----------
|
||||
|
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send_buffer: entity work.pp_fifo
|
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generic map(
|
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DEPTH => FIFO_DEPTH,
|
||||
WIDTH => 8
|
||||
) port map(
|
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clk => clk,
|
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reset => reset,
|
||||
full => send_buffer_full,
|
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empty => send_buffer_empty,
|
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data_in => send_buffer_input,
|
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data_out => send_buffer_output,
|
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push => send_buffer_push,
|
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pop => send_buffer_pop
|
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);
|
||||
|
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recv_buffer: entity work.pp_fifo
|
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generic map(
|
||||
DEPTH => FIFO_DEPTH,
|
||||
WIDTH => 8
|
||||
) port map(
|
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clk => clk,
|
||||
reset => reset,
|
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full => recv_buffer_full,
|
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empty => recv_buffer_empty,
|
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data_in => recv_buffer_input,
|
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data_out => recv_buffer_output,
|
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push => recv_buffer_push,
|
||||
pop => recv_buffer_pop
|
||||
);
|
||||
|
||||
---------- Wishbone Interface ----------
|
||||
|
||||
wishbone: process(clk)
|
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begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
wb_ack_out <= '0';
|
||||
wb_state <= IDLE;
|
||||
send_buffer_push <= '0';
|
||||
recv_buffer_pop <= '0';
|
||||
sample_clk_divisor <= (others => '0');
|
||||
irq_recv_enable <= '0';
|
||||
irq_tx_ready_enable <= '0';
|
||||
else
|
||||
case wb_state is
|
||||
when IDLE =>
|
||||
if wb_cyc_in = '1' and wb_stb_in = '1' then
|
||||
if wb_we_in = '1' then -- Write to register
|
||||
if wb_adr_in = x"000" then
|
||||
send_buffer_input <= wb_dat_in;
|
||||
send_buffer_push <= '1';
|
||||
elsif wb_adr_in = x"018" then
|
||||
sample_clk_divisor <= wb_dat_in;
|
||||
elsif wb_adr_in = x"020" then
|
||||
irq_recv_enable <= wb_dat_in(0);
|
||||
irq_tx_ready_enable <= wb_dat_in(1);
|
||||
end if;
|
||||
|
||||
-- Invalid writes are acked and ignored.
|
||||
wb_ack_out <= '1';
|
||||
wb_state <= WRITE_ACK;
|
||||
else -- Read from register
|
||||
if wb_adr_in = x"008" then
|
||||
recv_buffer_pop <= '1';
|
||||
elsif wb_adr_in = x"010" then
|
||||
wb_dat_out <= x"0" & send_buffer_full & recv_buffer_full &
|
||||
send_buffer_empty & recv_buffer_empty;
|
||||
wb_ack_out <= '1';
|
||||
elsif wb_adr_in = x"018" then
|
||||
wb_dat_out <= sample_clk_divisor;
|
||||
wb_ack_out <= '1';
|
||||
elsif wb_adr_in = x"020" then
|
||||
wb_dat_out <= (0 => irq_recv_enable,
|
||||
1 => irq_tx_ready_enable,
|
||||
others => '0');
|
||||
wb_ack_out <= '1';
|
||||
else
|
||||
wb_dat_out <= (others => '0');
|
||||
wb_ack_out <= '1';
|
||||
end if;
|
||||
wb_state <= READ_ACK;
|
||||
end if;
|
||||
end if;
|
||||
when WRITE_ACK =>
|
||||
send_buffer_push <= '0';
|
||||
|
||||
if wb_stb_in = '0' then
|
||||
wb_ack_out <= '0';
|
||||
wb_state <= IDLE;
|
||||
end if;
|
||||
when READ_ACK =>
|
||||
if recv_buffer_pop = '1' then
|
||||
recv_buffer_pop <= '0';
|
||||
else
|
||||
wb_dat_out <= recv_buffer_output;
|
||||
wb_ack_out <= '1';
|
||||
end if;
|
||||
|
||||
if wb_stb_in = '0' then
|
||||
wb_ack_out <= '0';
|
||||
wb_state <= IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process wishbone;
|
||||
|
||||
end architecture behaviour;
|
||||
@ -1,90 +0,0 @@
|
||||
-- The Potato Processor - A simple processor for FPGAs
|
||||
-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package pp_utilities is
|
||||
|
||||
--! Converts a boolean to an std_logic.
|
||||
function to_std_logic(input : in boolean) return std_logic;
|
||||
|
||||
-- Checks if a number is 2^n:
|
||||
function is_pow2(input : in natural) return boolean;
|
||||
|
||||
--! Calculates log2 with integers.
|
||||
function log2(input : in natural) return natural;
|
||||
|
||||
-- Gets the value of the sel signals to the wishbone interconnect for the specified
|
||||
-- operand size and address.
|
||||
function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
|
||||
return std_logic_vector;
|
||||
|
||||
end package pp_utilities;
|
||||
|
||||
package body pp_utilities is
|
||||
|
||||
function to_std_logic(input : in boolean) return std_logic is
|
||||
begin
|
||||
if input then
|
||||
return '1';
|
||||
else
|
||||
return '0';
|
||||
end if;
|
||||
end function to_std_logic;
|
||||
|
||||
function is_pow2(input : in natural) return boolean is
|
||||
variable c : natural := 1;
|
||||
begin
|
||||
for i in 0 to 31 loop
|
||||
if input = c then
|
||||
return true;
|
||||
end if;
|
||||
|
||||
c := c * 2;
|
||||
end loop;
|
||||
|
||||
return false;
|
||||
end function is_pow2;
|
||||
|
||||
function log2(input : in natural) return natural is
|
||||
variable retval : natural := 0;
|
||||
variable temp : natural := input;
|
||||
begin
|
||||
while temp > 1 loop
|
||||
retval := retval + 1;
|
||||
temp := temp / 2;
|
||||
end loop;
|
||||
|
||||
return retval;
|
||||
end function log2;
|
||||
|
||||
function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
|
||||
return std_logic_vector is
|
||||
begin
|
||||
case size is
|
||||
when b"01" =>
|
||||
case address(1 downto 0) is
|
||||
when b"00" =>
|
||||
return b"0001";
|
||||
when b"01" =>
|
||||
return b"0010";
|
||||
when b"10" =>
|
||||
return b"0100";
|
||||
when b"11" =>
|
||||
return b"1000";
|
||||
when others =>
|
||||
return b"0001";
|
||||
end case;
|
||||
when b"10" =>
|
||||
if address(1) = '0' then
|
||||
return b"0011";
|
||||
else
|
||||
return b"1100";
|
||||
end if;
|
||||
when others =>
|
||||
return b"1111";
|
||||
end case;
|
||||
end function wb_get_data_sel;
|
||||
|
||||
end package body pp_utilities;
|
||||
Binary file not shown.
Binary file not shown.
@ -1,135 +0,0 @@
|
||||
-- Sim console UART, provides the same interface as potato UART by
|
||||
-- Kristian Klomsten Skordal.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
use work.sim_console.all;
|
||||
|
||||
--! @brief Simple UART module.
|
||||
--! The following registers are defined:
|
||||
--! |--------------------|--------------------------------------------|
|
||||
--! | Address | Description |
|
||||
--! |--------------------|--------------------------------------------|
|
||||
--! | 0x00 | Transmit register (write-only) |
|
||||
--! | 0x08 | Receive register (read-only) |
|
||||
--! | 0x10 | Status register (read-only) |
|
||||
--! | 0x18 | Sample clock divisor register (dummy) |
|
||||
--! | 0x20 | Interrupt enable register (read/write) |
|
||||
--! |--------------------|--------------------------------------------|
|
||||
--!
|
||||
--! The status register contains the following bits:
|
||||
--! - Bit 0: receive buffer empty
|
||||
--! - Bit 1: transmit buffer empty
|
||||
--! - Bit 2: receive buffer full
|
||||
--! - Bit 3: transmit buffer full
|
||||
--!
|
||||
--! Interrupts are enabled by setting the corresponding bit in the interrupt
|
||||
--! enable register. The following bits are available:
|
||||
--! - Bit 0: data received (receive buffer not empty)
|
||||
--! - Bit 1: ready to send data (transmit buffer empty)
|
||||
entity pp_soc_uart is
|
||||
generic(
|
||||
FIFO_DEPTH : natural := 64 --Unused
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
-- UART ports:
|
||||
txd : out std_logic;
|
||||
rxd : in std_logic;
|
||||
|
||||
-- Interrupt signal:
|
||||
irq : out std_logic;
|
||||
|
||||
-- Wishbone ports:
|
||||
wb_adr_in : in std_logic_vector(11 downto 0);
|
||||
wb_dat_in : in std_logic_vector( 7 downto 0);
|
||||
wb_dat_out : out std_logic_vector( 7 downto 0);
|
||||
wb_we_in : in std_logic;
|
||||
wb_cyc_in : in std_logic;
|
||||
wb_stb_in : in std_logic;
|
||||
wb_ack_out : out std_logic
|
||||
);
|
||||
end entity pp_soc_uart;
|
||||
|
||||
architecture behaviour of pp_soc_uart is
|
||||
|
||||
signal sample_clk_divisor : std_logic_vector(7 downto 0);
|
||||
|
||||
-- IRQ enable signals:
|
||||
signal irq_recv_enable, irq_tx_ready_enable : std_logic := '0';
|
||||
|
||||
-- Wishbone signals:
|
||||
type wb_state_type is (IDLE, WRITE_ACK, READ_ACK);
|
||||
signal wb_state : wb_state_type;
|
||||
signal wb_ack : std_logic; --! Wishbone acknowledge signal
|
||||
|
||||
begin
|
||||
|
||||
wb_ack_out <= wb_ack and wb_cyc_in and wb_stb_in;
|
||||
|
||||
-- For the sim console, the transmit buffer is always empty, so always
|
||||
-- interrupt if enabled. No recieve interrupt.
|
||||
irq <= irq_tx_ready_enable;
|
||||
|
||||
wishbone: process(clk)
|
||||
variable sim_tmp : std_logic_vector(63 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset = '1' then
|
||||
wb_ack <= '0';
|
||||
wb_state <= IDLE;
|
||||
sample_clk_divisor <= (others => '0');
|
||||
irq_recv_enable <= '0';
|
||||
irq_tx_ready_enable <= '0';
|
||||
else
|
||||
case wb_state is
|
||||
when IDLE =>
|
||||
if wb_cyc_in = '1' and wb_stb_in = '1' then
|
||||
if wb_we_in = '1' then -- Write to register
|
||||
if wb_adr_in(11 downto 0) = x"000" then
|
||||
sim_console_write(x"00000000000000" & wb_dat_in);
|
||||
elsif wb_adr_in(11 downto 0) = x"018" then
|
||||
sample_clk_divisor <= wb_dat_in;
|
||||
elsif wb_adr_in(11 downto 0) = x"020" then
|
||||
irq_recv_enable <= wb_dat_in(0);
|
||||
irq_tx_ready_enable <= wb_dat_in(1);
|
||||
end if;
|
||||
wb_ack <= '1';
|
||||
wb_state <= WRITE_ACK;
|
||||
else -- Read from register
|
||||
if wb_adr_in(11 downto 0) = x"008" then
|
||||
sim_console_read(sim_tmp);
|
||||
wb_dat_out <= sim_tmp(7 downto 0);
|
||||
elsif wb_adr_in(11 downto 0) = x"010" then
|
||||
sim_console_poll(sim_tmp);
|
||||
wb_dat_out <= "00000" & sim_tmp(0) & '1' & not sim_tmp(0);
|
||||
elsif wb_adr_in(11 downto 0) = x"018" then
|
||||
wb_dat_out <= sample_clk_divisor;
|
||||
elsif wb_adr_in(11 downto 0) = x"020" then
|
||||
wb_dat_out <= (0 => irq_recv_enable,
|
||||
1 => irq_tx_ready_enable,
|
||||
others => '0');
|
||||
else
|
||||
wb_dat_out <= (others => '0');
|
||||
end if;
|
||||
wb_ack <= '1';
|
||||
wb_state <= READ_ACK;
|
||||
end if;
|
||||
end if;
|
||||
when WRITE_ACK|READ_ACK =>
|
||||
if wb_stb_in = '0' then
|
||||
wb_ack <= '0';
|
||||
wb_state <= IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process wishbone;
|
||||
|
||||
end architecture behaviour;
|
||||
Loading…
Reference in New Issue