Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.
Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
- Changing use of others in core files to satisfy VCS
- Adding workaround for VCS subtype constraint inconsistencies in common.vhdl
Signed-off-by: Jonathan Balkind <jbalkind@princeton.edu>
This adds one-cycle latches to the various resets out of the soc and
into the various core modules. It *seems* to help vivado P&R a bit
and has shown to avoid timing violations under some circumstances.
Interestingly those resets never seem to appear in the bad timing
path. It looks like those long resets simply impose placement
constraints that Vivado satisfies at the expense of timing elsewhere.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
When using litedram, request a much longer PLL reset. This seems to
help get rid of all the grabled output after config.
Also use the clean system_rst out of litedram as our source of reset
for the rest of the SoC (it is synchronized with system_clk and takes
pll_locked into account already)
In some cases we need to keep the reset held for much longer,
so use counters rather than shift registers.
Additionally, some signals such as ext_rst and pll_locked
or signals going from the ext_clk domain to the pll_clk
domain need to be treated as async, and testing them without
synchronizers is asking for trouble.
Finally, make the external reset also reset the PLL.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Things have changed a bit in upstream LiteX. LiteDRAM now exposes a
wishbone for the CSRs for example.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This fixes a bug where a store that hits in the dcache immediately
following a dcbz has its write to the cache RAM suppressed (but not
its write to memory). If a load to the same location comes along
before the cache line gets replaced, the load will return incorrect
data.
Fixes: 4db1676ef8 ("dcache: Don't assert on dcbz cache hit")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
The rx synchronizers were ... non existent. Someone forgot to add
a if rising_edge(clk) to the process.
For tx, ensure that we have a default value so that TX stays high
from TPGA configuration to the reset being sampled on the first clock
cycle.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The pp_fifo decides whether top = bottom means empty or full based
on whether the previous operation was a push or a pop.
If the fifo performs both in one cycle, it sets the previous op to
pop. That means that a full fifo being added a character and removed
one at the same time becomes empty.
Instead, just leave the previous op alone. If the fifo was empty, it
remains so, if it was full ditto.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
console.c goes to a new lib/ where we'll store other general utilities
and console.h goes to include/
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
It makes things a bit more standard and a bit nicer to read
without all those strlen(). Also console.c takes care of adding
the carriage returns before the linefeeds.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Make putchar() match a standard prototype and add puts()
Also make puts() add carriage returns before linefeeds so the
users don't have to do it all over the place.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The ghdl packaged in Fedora 31 doesn't like a port map of the form
"rst => rst or core_reset", so this works around the problem by
doing the OR in a separate statement.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds support for initializing the memory controller from microwatt
rather than using a built-in RiscV processor. This might require some
fixes to LiteX and LiteDRAM (they haven't been merged as of this commit
yet).
This is enabled in the shipped generated files and can be changed via
modifying the generator script to pass False to "mw_init"
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This uses the new header files for register definitions and
extracts the core frequency from syscon rather than hard coding it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This contains C definitions for various Microwatt internal MMIOs
and a set of accessors.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
These provides some info about the SoC (though it's still somewhat
incomplete and needs more work, see comments).
There's also a control register for selecting DRAM vs. BRAM at 0
(and for soft-resetting the SoC but that isn't wired up yet).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The old toplevel.vhdl becomes top-generic.vhdl, which is to be used
by platforms that do not have a litedram option.
Arty has its own top-arty.vhdl which supports litedram and is now
hooked up
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This adds the PID register and repurposes SPR 720 as the PRTBL
register, which points to the base of the process table. There
doesn't seem to be any point to implementing the partition table given
that we don't have hypervisor mode.
The MMU caches entry 0 of the process table internally (in pgtbl3)
plus the entry indexed by the value in the PID register (pgtbl0).
Both caches are invalidated by a tlbie[l] with RIC=2 or by a move to
PRTBL. The pgtbl0 cache is invalidated by a move to PID. The dTLB
and iTLB are cleared by a move to either PRTBL or PID.
Which of the two page table root pointers is used (pgtbl0 or pgtbl3)
depends on the MSB of the address being translated. Since the segment
checking ensures that address(63) = address(62), this is sufficient to
map quadrants 0 and 3.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Slbia (with IH=7) is used in the Linux kernel to flush the ERATs
(our iTLB/dTLB), so make it do that.
This moves the logic to work out whether to flush a single entry
or the whole TLB from dcache and icache into mmu. We now invalidate
all dTLB and iTLB entries when the AP (actual pagesize) field of
RB is non-zero on a tlbie[l], as well as when IS is non-zero.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Since setting MSR[PR] = 1 forces instruction translation on, we need
to set up translations for the problem state code to use.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds tests of instruction translation to the mmu test.
This also clears the BSS and improves the linker script.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This hooks up the connections so that an OP_FETCH_FAILED coming down
to loadstore1 will get sent to the MMU for it to do a radix tree walk
for the instruction address. The MMU then sends the resulting PTE to
the icache module to be installed in the iTLB. If no valid PTE can
be found, the MMU sends an error signal back to loadstore1 which sends
it on to execute1 to generate an ISI.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds a direct-mapped TLB to the icache, with 64 entries by default.
Execute1 now sends a "virt_mode" signal from MSR[IR] to fetch1 along
with redirects to indicate whether instruction addresses should be
translated through the TLB, and fetch1 sends that on to icache.
Similarly a "priv_mode" signal is sent to indicate the privilege
mode for instruction fetches. This means that changes to MSR[IR]
or MSR[PR] don't take effect until the next redirect, meaning an
isync, rfid, branch, etc.
The icache uses a hash of the effective address (i.e. next instruction
address) to index the TLB. The hash is an XOR of three fields of the
address; with a 64-entry TLB, the fields are bits 12--17, 18--23 and
24--29 of the address. TLB invalidations simply invalidate the
indexed TLB entry without checking the contents.
If the icache detects a TLB miss with virt_mode=1, it will send a
fetch_failed indication through fetch2 to decode1, which will turn it
into a special OP_FETCH_FAILED opcode with unit=LDST. That will get
sent down to loadstore1 which will currently just raise a Instruction
Storage Interrupt (0x400) exception.
One bit in the PTE obtained from the TLB is used to check whether an
instruction access is allowed -- the privilege bit (bit 3). If bit 3
is 1 and priv_mode=0, then a fetch_failed indication is sent down to
fetch2 and to decode1, which generates an OP_FETCH_FAILED. Any PTEs
with PTE bit 0 (EAA[3]) clear or bit 8 (R) clear should not be put
into the iTLB since such PTEs would not allow execution by any
context.
Tlbie operations get sent from mmu to icache over a new connection.
Unfortunately the privileged instruction tests are broken for now.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds tests to check that the MMU and dTLB are translating
addresses and checking permissions correctly.
We use a simple 2-level radix tree. The radix tree maps 2GB of
address space and has a 1024-entry page directory pointing to
512-entry page table pages.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This removes the hack where the tlbie instruction could be used to
load entries directly into the dTLB, because we don't report the
correct DSISR values for accesses that hit software-loaded dTLB
entries and have privilege or permission errors.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This is required by the architecture. It means that the error bits
reported in DSISR or SRR1 now come from the permission/RC check done
on the refetched PTE rather than the TLB entry. Unfortunately that
somewhat breaks the software-loaded TLB mode of operation in that
DSISR/SRR1 always report no PTE rather than permission error or
RC failure.
This also restructures the loadstore1 state machine a bit, combining
the FIRST_ACK_WAIT and LAST_ACK_WAIT states into a single state and
the MMU_LOOKUP_1ST and MMU_LOOKUP_LAST states likewise. We now have a
'dwords_done' bit to say whether the first transfer of two (for an
unaligned access) has been done.
The cache paradox error (where a non-cacheable access finds a hit in
the cache) is now the only cause of DSI from the dcache. This should
probably be a machine check rather than DSI in fact.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
A data segment interrupt (DSegI) occurs when an address to be
translated by the MMU is outside the range of the radix tree
or the top two bits of the address (the quadrant) are 01 or 10.
This is detected in a new state of the MMU state machine, and
is sent back to loadstore1 as an error, which sends it on to
execute1 to generate an interrupt to the 0x380 vector.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard
Paul Mackerras