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fpu-init
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icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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1124 Commits (35e0dbed345011bafb651fa7d168de550e6fd6e7)
 

Author SHA1 Message Date
Paul Mackerras 35e0dbed34
Merge pull request #353 from tianrui-wei/master 
fix: fix icache_tb not finishing correctly
 3 years ago
Michael Neuling cd52390bf1
Merge pull request #373 from antonblanchard/icache-insn-u-state 
icache: Don't output X on i_out.insn
 3 years ago
Michael Neuling b983d5080e
Merge pull request #376 from antonblanchard/loadstore-init 
loadstore1: reduce U state being output
 3 years ago
Michael Neuling d4db331467
Merge pull request #374 from antonblanchard/icache-unused-sig 
core: Remove unused icache_inv signal
 3 years ago
Michael Neuling ee5e3778ed
Merge pull request #364 from shenki/readme-updates 
Readme updates
 3 years ago
Michael Neuling c43692f4c7
Merge pull request #372 from antonblanchard/dcache-unused-sig 
dcache: remove unused do_write signal
 3 years ago
Michael Neuling 956df2c863
Merge pull request #371 from antonblanchard/unused-sig 
execute1: sub_mux_sel and result_mux_sel are unused
 3 years ago
Michael Neuling 3627f102db
Merge pull request #370 from antonblanchard/divider-init 
divider: Fix d_out.overflow U state issue
 3 years ago
Paul Mackerras 6e1e763c02
Merge pull request #368 from antonblanchard/icache-pmu-events 
icache: Hook up PMU events
 3 years ago
Anton Blanchard 1047239a37
Merge pull request #377 from antonblanchard/fpu-init 
fpu: Reduce uninitialised signals
 3 years ago
Anton Blanchard 9d35340bb1 fpu: Reduce uninitialised signals 
Reduce uninitialised signals coming out of the FPU.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Michael Neuling b82eea5933
Merge pull request #366 from antonblanchard/hello-world-bss 
Zero BSS in hello world test
 3 years ago
Anton Blanchard d3aff67fa7
Merge pull request #375 from antonblanchard/core_debug-init 
core_debug: Initialise gspr_index
 3 years ago
Anton Blanchard b47b71821e loadstore1: reduce U state being output 
While these signals should only be read when valid is true, they
are only a small number of bits and we want to reduce the amount of
U/X state bouncing around the chip.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 71d4b5ed20 core_debug: Initialise gspr_index 
Another case of U state being driven out of a module.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard a527d9b959 core: Remove unused icache_inv signal 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard e7f0a7c7ac icache: Don't output X on i_out.insn 
decode1 has a lot of logic that uses i_out.insn without first looking at
i_iout.valid. Play it safe and never output X state.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 39220be311 dcache: remove unused do_write signal 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 843361f2be execute1: sub_mux_sel and result_mux_sel are unused 
Remove them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard d3a7517318 divider: Fix d_out.overflow U state issue 
While we should only look at this when d_out.valid = 1, we may as remove
some U state across interfaces.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 1ff852b012
Merge pull request #369 from antonblanchard/loadstore-pmu-init 
loadstore1: Initialise PMU events
 3 years ago
Anton Blanchard e2438071a1 loadstore1: Initialise PMU events 
The loadstore1 PMU events are U state until a load and a store completes.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard b7c4d3c5c3
Merge pull request #367 from antonblanchard/fpu-typo 
fpu: Fix capitalisation of Execute1ToFPUType
 3 years ago
Anton Blanchard f06abb67ad icache: Hook up PMU events 
We weren't connecting the icache PMU events up.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 64d2def0c6 fpu: Fix capitalisation of Execute1ToFPUType 
While this is not an issue in VHDL, I noticed this when running
a script over the source and we may as well fix it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard ff442d1bdb Zero BSS in hello world test 
While trying to reduce U/X state issues, I notice that our BSS is not
being initialised in the hello world test.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard b8fc5636a4
Merge pull request #365 from antonblanchard/less-fpga-init 
Remove some FPGA style signal inits
 3 years ago
Anton Blanchard ebdddcc402 Remove some FPGA style signal inits 
These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard a750365ffa Remove some FPGA style signal inits 
These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Joel Stanley 9ec22af256 README: Add Linux on Microwatt instructions 
These instructions are similar to those at

 https://ozlabs.org/~joel/microwatt/README

except they describe how to build the artifacts from scratch instead of
downloading them.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 3 years ago
Joel Stanley a31725d989 README: Add uart to fusesoc instructions 
The SoC defaults to using the uart16550 so provide instructions on how
to fetch that library when seetting up fusesoc.

Also remove the text about a working directory; fusesoc doesn't need
one.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 3 years ago
Michael Neuling f5e06c2d4b
Merge pull request #361 from antonblanchard/alt-reset-address 
Allow ALT_RESET_ADDRESS to be overridden
 3 years ago
Anton Blanchard 948f6f43a7 Allow ALT_RESET_ADDRESS to be overridden 
This allows us to boot from flash for example.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Michael Neuling 8bf48ac094
Merge pull request #360 from antonblanchard/log2ceil-issue 
wishbone_bram_wrapper ram_addr_bits is 1 bit off
 3 years ago
Anton Blanchard b5accb78b2 wishbone_bram_wrapper ram_addr_bits is 1 bit off 
log2ceil() returns the number of bits required to store a value, so we
need to pass in memory_size-1, not memory_size.

Every other user of log2ceil() gets this right.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Michael Neuling 30fd936c12
Merge pull request #358 from antonblanchard/unused-sig 
Remove unused sequential signal from Fetch1ToIcacheType
 3 years ago
Michael Neuling af1b76d944
Merge pull request #356 from antonblanchard/fpu-constant 
fpu: Make inverse_table a constant
 3 years ago
Michael Neuling 9b96ab730c
Merge pull request #357 from antonblanchard/xics-warning 
xics: Fix warning when comparing two std_ulogic_vectors
 3 years ago
Anton Blanchard 0b39947f8d Remove unused sequential signal from Fetch1ToIcacheType 
GHDL synthesis is flagging a warning about this.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 00bf0af21c xics: Fix warning when comparing two std_ulogic_vectors 
Use unsigned() to make it clear what we are doing.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 50b4cb9423 fpu: Make inverse_table a constant 
GHDL synthesis is complaining that inverse_table is never stored to.
Change it to a constant.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Tianrui Wei 844ca0e6b5
fix: fix icache_tb not finishing correctly 
Setting icache to be privileged and accessing physical memory directly.
And set big_endian to 0 to correspond to the testbench result.

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
 3 years ago
Michael Neuling f01f3d233a
Merge pull request #352 from mkj/static-urjtag 
mw_debug: Add STATIC_URJTAG flag
 3 years ago
Matt Johnston c0c00d05bc mw_debug: Add STATIC_URJTAG flag 
Revert to linking dynamically by default, can statically link with
`make STATIC_URJTAG=1`

Fixes #351

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 3 years ago
Michael Neuling ffcdaaa92d
Update the README Issues (#350) 
We've had these for a while now:
 - D/I cache
 - GPR bypassing
 - Supervisor state (and can boot linux)

We still need Vector/VMX/VSX (and probably some other things)

Signed-off-by: Michael Neuling <mikey@neuling.org>
 3 years ago
Michael Neuling b4770197a2
Merge pull request #349 from madscientist159/master 
Extend LiteDRAM VHDL wrapper to allow more than one clock line
 3 years ago
Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line 
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
 3 years ago
Michael Neuling 2b97fb0bf3
Merge pull request #348 from paulusmack/reduce 
Reduce LUT usage
 3 years ago
Paul Mackerras 0aa898c7a6 xics: Rework the irq_gen process 
At present, the loop in the irq_gen process generates a chain of
comparators and other logic to work out the source number and priority
of the most-favoured (lowest priority number) pending interrupt.
This replaces that chain with (1) logic to generate an array of bits,
one per priority, indicating whether any interrupt is pending at that
priority, (2) a priority encoder to select the most favoured priority
with an interrupt pending, (3) logic to generate an array of bits, one
per source, indicating whether an interrupt is pending at the priority
calculated in step 2, and (4) a priority encoder to work out the
lowest numbered source that has an interrupt pending at the selected
priority.  This reduces LUT utilization.

The priority encoder function implemented here uses the optimized
count-leading-zeroes logic from helpers.vhdl.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 3 years ago
Paul Mackerras 1720a0584a Use alternative count-leading-zeroes algorithm in the FPU and LSU 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 3 years ago