Make caches 1 way

asic-3
Anton Blanchard 3 years ago
parent 7da4977028
commit e70d7f0a60

@ -26,10 +26,10 @@ entity toplevel is
HAS_UART1 : boolean := false; HAS_UART1 : boolean := false;
HAS_JTAG : boolean := true; HAS_JTAG : boolean := true;
ICACHE_NUM_LINES : natural := 4; ICACHE_NUM_LINES : natural := 4;
ICACHE_NUM_WAYS : natural := 2; ICACHE_NUM_WAYS : natural := 1;
ICACHE_TLB_SIZE : natural := 4; ICACHE_TLB_SIZE : natural := 4;
DCACHE_NUM_LINES : natural := 4; DCACHE_NUM_LINES : natural := 4;
DCACHE_NUM_WAYS : natural := 2; DCACHE_NUM_WAYS : natural := 1;
DCACHE_TLB_SET_SIZE : natural := 2; DCACHE_TLB_SET_SIZE : natural := 2;
DCACHE_TLB_NUM_WAYS : natural := 2; DCACHE_TLB_NUM_WAYS : natural := 2;
HAS_GPIO : boolean := true; HAS_GPIO : boolean := true;

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