Reset TB and DECR

We don't care what the values of TB and DECR are after reset, but we
don't want the X state to propagate to other parts of the chip.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
cache-tlb-parameters-2
Anton Blanchard 4 years ago committed by Anton Blanchard
parent 39c826aa46
commit e1bac4d6e7

@ -282,6 +282,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
r <= reg_type_init; r <= reg_type_init;
ctrl.tb <= (others => '0');
ctrl.dec <= (others => '0');
ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0'); ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
ctrl.irq_state <= WRITE_SRR0; ctrl.irq_state <= WRITE_SRR0;
else else

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