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Merge Makefile and Makefile.synth

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We still need to a way to our FPGA target on the command line, but this
at least gets us down to a common Makefile.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
jtag-port
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 6326efaca4
commit a9e7194de5
2 changed files with 74 additions and 92 deletions
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74
Makefile
Unescape Escape View File

@ -2,6 +2,12 @@ GHDL ?= ghdl
GHDLFLAGS=--std=08 --work=unisim GHDLFLAGS=--std=08 --work=unisim
CFLAGS=-O2 -Wall CFLAGS=-O2 -Wall


GHDLSYNTH ?= ghdl.so
YOSYS ?= yosys
NEXTPNR ?= nextpnr-ecp5
ECPPACK ?= ecppack
OPENOCD ?= openocd

# We need a version of GHDL built with either the LLVM or gcc backend. # We need a version of GHDL built with either the LLVM or gcc backend.
# Fedora provides this, but other distros may not. Another option is to use # Fedora provides this, but other distros may not. Another option is to use
# the Docker image. # the Docker image.
@ -23,6 +29,11 @@ PWD = $(shell pwd)
DOCKERARGS = run --rm -v $(PWD):/src:z -w /src DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
GHDL = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl GHDL = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
CC = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc CC = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
GHDLSYNTH = ghdl
YOSYS = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:beta yosys
NEXTPNR = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
ECPPACK = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:trellis ecppack
OPENOCD = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
endif endif


all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \ all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
@ -56,8 +67,6 @@ SOC_SIM_LINK=$(patsubst %,-Wl$(comma)%,$(SOC_SIM_OBJ_FILES))
CORE_TBS=multiply_tb divider_tb rotator_tb countzero_tb CORE_TBS=multiply_tb divider_tb rotator_tb countzero_tb
SOC_TBS=core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb SOC_TBS=core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb


$(processes): %_processes: tests/%.o main.c

$(SOC_TBS): %: $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $(SOC_SIM_OBJ_FILES) %.vhdl $(SOC_TBS): %: $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $(SOC_SIM_OBJ_FILES) %.vhdl
$(GHDL) -c $(GHDLFLAGS) $(SOC_SIM_LINK) $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $@.vhdl -e $@ $(GHDL) -c $(GHDLFLAGS) $(SOC_SIM_LINK) $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $@.vhdl -e $@


@ -67,6 +76,61 @@ $(CORE_TBS): %: $(CORE_FILES) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
$(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@ $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@


# Hello world
GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=8192 -gRAM_INIT_FILE=hello_world/hello_world.hex

# Micropython
#GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=393216 -gRAM_INIT_FILE=micropython/firmware.hex

# OrangeCrab with ECP85
GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000
LPF=constraints/orange-crab.lpf
PACKAGE=CSFBGA285
NEXTPNR_FLAGS=--um5g-85k --freq 50
OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg

# ECP5-EVN
#GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=12000000 -gCLK_FREQUENCY=12000000
#LPF=constraints/ecp5-evn.lpf
#PACKAGE=CABGA381
#NEXTPNR_FLAGS=--um5g-85k --freq 12
#OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
#OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg

CLKGEN=fpga/clk_gen_bypass.vhd
TOPLEVEL=fpga/top-generic.vhdl
DMI_DTM=dmi_dtm_dummy.vhdl

FPGA_FILES = $(CORE_FILES) $(SOC_FILES)
FPGA_FILES += fpga/soc_reset.vhdl fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd
FPGA_FILES += fpga/main_bram.vhdl

SYNTH_FILES = $(CORE_FILES) $(SOC_FILES) $(FPGA_FILES) $(CLKGEN) $(TOPLEVEL) $(DMI_DTM)

microwatt.json: $(SYNTH_FILES)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(SYNTH_FILES) -e toplevel; synth_ecp5 -json $@"

microwatt.v: $(SYNTH_FILES)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(SYNTH_FILES) -e toplevel; write_verilog $@"

# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
verilator -O3 --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
make -C obj_dir -f Vmicrowatt.mk
@cp -f obj_dir/microwatt-verilator microwatt-verilator

microwatt_out.config: microwatt.json $(LPF)
$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)

microwatt.bit: microwatt_out.config
$(ECPPACK) --svf microwatt.svf $< $@

microwatt.svf: microwatt.bit

prog: microwatt.svf
$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"

tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out))) tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out))) tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))


@ -98,6 +162,9 @@ _clean:
rm -f TAGS rm -f TAGS
rm -f scripts/mw_debug/*.o rm -f scripts/mw_debug/*.o
rm -f scripts/mw_debug/mw_debug rm -f scripts/mw_debug/mw_debug
rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
rm -f microwatt.v microwatt-verilator
rm -rf obj_dir/


clean: _clean clean: _clean
make -f scripts/mw_debug/Makefile clean make -f scripts/mw_debug/Makefile clean
@ -111,3 +178,6 @@ distclean: _clean
rm -f litedram/gen-src/sdram_init/*~ rm -f litedram/gen-src/sdram_init/*~
make -f scripts/mw_debug/Makefile distclean make -f scripts/mw_debug/Makefile distclean
make -f hello_world/Makefile distclean make -f hello_world/Makefile distclean

.PHONY: all prog check check_light clean distclean
.PRECIOUS: microwatt.json microwatt_out.config microwatt.bit

88
Makefile.synth
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@ -1,88 +0,0 @@
# Use local tools
#GHDLSYNTH = ghdl.so
#YOSYS = yosys
#NEXTPNR = nextpnr-ecp5
#ECPPACK = ecppack
#OPENOCD = openocd

# Use Docker images
DOCKER=docker
#DOCKER=podman
#
PWD = $(shell pwd)
DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
#
GHDLSYNTH = ghdl
YOSYS = $(DOCKER) $(DOCKERARGS) ghdl/synth:beta yosys
NEXTPNR = $(DOCKER) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
ECPPACK = $(DOCKER) $(DOCKERARGS) ghdl/synth:trellis ecppack
OPENOCD = $(DOCKER) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd


# Hello world
GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=8192 -gRAM_INIT_FILE=hello_world/hello_world.hex

# Micropython
#GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=393216 -gRAM_INIT_FILE=micropython/firmware.hex


# OrangeCrab with ECP85
#GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000
#LPF=constraints/orange-crab.lpf
#PACKAGE=CSFBGA285
#NEXTPNR_FLAGS=--um5g-85k --freq 50
#OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
#OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg

# ECP5-EVN
GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=12000000 -gCLK_FREQUENCY=12000000
LPF=constraints/ecp5-evn.lpf
PACKAGE=CABGA381
NEXTPNR_FLAGS=--um5g-85k --freq 12
OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg

VHDL_FILES = fpga/soc_reset.vhdl fpga/clk_gen_bypass.vhd decode_types.vhdl
VHDL_FILES += common.vhdl wishbone_types.vhdl wishbone_debug_master.vhdl
VHDL_FILES += wishbone_arbiter.vhdl cache_ram.vhdl utils.vhdl plru.vhdl
VHDL_FILES += helpers.vhdl mmu.vhdl dcache.vhdl core_debug.vhdl fetch1.vhdl fetch2.vhdl
VHDL_FILES += register_file.vhdl insn_helpers.vhdl multiply.vhdl divider.vhdl
VHDL_FILES += logical.vhdl crhelpers.vhdl countzero.vhdl rotator.vhdl
VHDL_FILES += ppc_fx_insns.vhdl execute1.vhdl decode1.vhdl cr_file.vhdl
VHDL_FILES += writeback.vhdl loadstore1.vhdl icache.vhdl cr_hazard.vhdl
VHDL_FILES += gpr_hazard.vhdl control.vhdl decode2.vhdl core.vhdl
VHDL_FILES += fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd dmi_dtm_dummy.vhdl
VHDL_FILES += fpga/main_bram.vhdl wishbone_bram_wrapper.vhdl syscon.vhdl
VHDL_FILES += xics.vhdl soc.vhdl fpga/top-generic.vhdl

all: microwatt.bit

microwatt.json: $(VHDL_FILES)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(VHDL_FILES) -e toplevel; synth_ecp5 -json $@"

microwatt.v: $(VHDL_FILES)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(VHDL_FILES) -e toplevel; write_verilog $@"

microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
#verilator -O3 -Wall --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
verilator -O3 --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
make -C obj_dir -f Vmicrowatt.mk
@cp -f obj_dir/microwatt-verilator microwatt-verilator

microwatt_out.config: microwatt.json $(LPF)
$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)

microwatt.bit: microwatt_out.config
$(ECPPACK) --svf microwatt.svf $< $@

microwatt.svf: microwatt.bit

prog: microwatt.svf
$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"

clean:
@rm -f work-obj08.cf *.bit *.json *.svf *.config microwatt.v microwatt-verilator
@rm -rf obj_dir/

.PHONY: clean prog
.PRECIOUS: microwatt.json microwatt_out.config microwatt.bit
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