Use simulated UART in core test bench

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
nia-debug
Benjamin Herrenschmidt 5 years ago committed by Anton Blanchard
parent 1b9c6f4647
commit 8bfd6e5eae

@ -12,7 +12,7 @@ all: $(all)
$(GHDL) -a $(GHDLFLAGS) $< $(GHDL) -a $(GHDLFLAGS) $<


common.o: decode_types.o common.o: decode_types.o
core_tb.o: common.o wishbone_types.o core.o simple_ram_behavioural.o core_tb.o: common.o wishbone_types.o core.o simple_ram_behavioural.o sim_uart.o
core.o: common.o wishbone_types.o fetch1.o fetch2.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o wishbone_arbiter.o core.o: common.o wishbone_types.o fetch1.o fetch2.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o wishbone_arbiter.o
cr_file.o: common.o cr_file.o: common.o
crhelpers.o: common.o crhelpers.o: common.o
@ -34,6 +34,7 @@ multiply.o: common.o decode_types.o ppc_fx_insns.o crhelpers.o
ppc_fx_insns.o: helpers.o ppc_fx_insns.o: helpers.o
register_file.o: common.o register_file.o: common.o
sim_console.o: sim_console.o:
sim_uart.o: sim_console.o
simple_ram_behavioural_helpers.o: simple_ram_behavioural_helpers.o:
simple_ram_behavioural_tb.o: wishbone_types.o simple_ram_behavioural.o simple_ram_behavioural_tb.o: wishbone_types.o simple_ram_behavioural.o
simple_ram_behavioural.o: wishbone_types.o simple_ram_behavioural_helpers.o simple_ram_behavioural.o: wishbone_types.o simple_ram_behavioural_helpers.o

@ -1,5 +1,7 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;


library work; library work;
use work.common.all; use work.common.all;
@ -11,8 +13,14 @@ end core_tb;
architecture behave of core_tb is architecture behave of core_tb is
signal clk, rst: std_logic; signal clk, rst: std_logic;


signal wishbone_in : wishbone_slave_out; signal wishbone_core_in : wishbone_slave_out;
signal wishbone_out : wishbone_master_out; signal wishbone_core_out : wishbone_master_out;

signal wishbone_ram_in : wishbone_slave_out;
signal wishbone_ram_out : wishbone_master_out;

signal wishbone_uart_in : wishbone_slave_out;
signal wishbone_uart_out : wishbone_master_out;


signal registers : regfile; signal registers : regfile;
signal terminate : std_ulogic; signal terminate : std_ulogic;
@ -22,12 +30,55 @@ architecture behave of core_tb is
begin begin
core_0: entity work.core core_0: entity work.core
generic map (SIM => true) generic map (SIM => true)
port map (clk => clk, rst => rst, wishbone_in => wishbone_in, port map (clk => clk, rst => rst, wishbone_in => wishbone_core_in,
wishbone_out => wishbone_out, registers => registers, terminate_out => terminate); wishbone_out => wishbone_core_out, registers => registers, terminate_out => terminate);


simple_ram_0: entity work.simple_ram_behavioural simple_ram_0: entity work.simple_ram_behavioural
generic map ( filename => "simple_ram_behavioural.bin", size => 524288) generic map ( filename => "simple_ram_behavioural.bin", size => 524288)
port map (clk => clk, rst => rst, wishbone_in => wishbone_out, wishbone_out => wishbone_in); port map (clk => clk, rst => rst, wishbone_in => wishbone_ram_out, wishbone_out => wishbone_ram_in);

simple_uart_0: entity work.sim_uart
port map ( clk => clk, reset => rst, wishbone_in => wishbone_uart_out, wishbone_out => wishbone_uart_in);


bus_process: process(wishbone_core_out, wishbone_ram_in, wishbone_uart_in)
-- Selected slave
type slave_type is (SLAVE_UART, SLAVE_MEMORY, SLAVE_NONE);
variable slave : slave_type;
begin
-- Simple address decoder
slave := SLAVE_NONE;
if wishbone_core_out.adr(31 downto 24) = x"00" then
slave := SLAVE_MEMORY;
elsif wishbone_core_out.adr(31 downto 24) = x"c0" then
if wishbone_core_out.adr(15 downto 12) = x"2" then
slave := SLAVE_UART;
end if;
end if;

-- Wishbone muxing:
-- Start with all master signals to all slaves, then override
-- cyc and stb accordingly
wishbone_ram_out <= wishbone_core_out;
wishbone_uart_out <= wishbone_core_out;
if slave = SLAVE_MEMORY then
wishbone_core_in <= wishbone_ram_in;
else
wishbone_ram_out.cyc <= '0';
wishbone_ram_out.stb <= '0';
end if;
if slave = SLAVE_UART then
wishbone_core_in <= wishbone_uart_in;
else
wishbone_uart_out.cyc <= '0';
wishbone_uart_out.stb <= '0';
end if;
if slave = SLAVE_NONE then
wishbone_core_in.dat <= (others => '1');
wishbone_core_in.ack <= wishbone_core_out.cyc and
wishbone_core_out.stb;
end if;
end process;


clk_process: process clk_process: process
begin begin

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