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@ -114,6 +114,7 @@ architecture behave of core_debug is
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signal do_dmi_log_rd : std_ulogic;
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signal do_dmi_log_rd : std_ulogic;
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signal dmi_read_log_data : std_ulogic;
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signal dmi_read_log_data : std_ulogic;
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signal dmi_read_log_data_1 : std_ulogic;
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signal dmi_read_log_data_1 : std_ulogic;
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signal log_trigger_delay : integer range 0 to 255 := 0;
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begin
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begin
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-- Single cycle register accesses on DMI except for GSPR data
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-- Single cycle register accesses on DMI except for GSPR data
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@ -152,9 +153,15 @@ begin
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if (rst) then
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if (rst) then
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stopping <= '0';
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stopping <= '0';
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terminated <= '0';
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terminated <= '0';
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log_trigger_delay <= 0;
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else
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else
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if do_log_trigger = '1' then
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if do_log_trigger = '1' or log_trigger_delay /= 0 then
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log_dmi_trigger(1) <= '1';
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if log_trigger_delay = 255 then
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log_dmi_trigger(1) <= '1';
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log_trigger_delay <= 0;
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else
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log_trigger_delay <= log_trigger_delay + 1;
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end if;
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end if;
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end if;
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-- Edge detect on dmi_req for 1-shot pulses
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-- Edge detect on dmi_req for 1-shot pulses
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dmi_req_1 <= dmi_req;
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dmi_req_1 <= dmi_req;
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