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Meeting Minutes 2022-05-12 2022-05-12

LibreBMC SIG Meeting

Meeting date: 12 May 2022 Access link: Meeting ID: 91597478078

Call to Order

Anti-trust Reminder

This is a reminder that all OpenPOWER Foundation activities are subject to strict compliance with the OpenPOWER Foundations Antitrust Guidelines. Each individual participant and attendee at this meeting is responsible for knowing the contents of the Antitrust Guidelines, and for complying with the Antitrust Guidelines. Copies of the Antitrust Guidelines are available at: Antitrust Guidelines

Meeting Recording

Meeting is being recorded



New faces so some introductions

  • Luke Leighton (Libre-SOC)
  • Daisuke Oka. Testing framework to port Intel Intrisics to OpenPOWER
  • Mohan Rao. Analog and mixed signal Integrity

New News

Any update?

Hardware Update

  • Lattice ECP5 version of DC-SCM

    • Still missing ethernet Phys, but they do have the ECP5. Covid outbreak stopped chips.
  • Xilinx Artix 7 version of DC-SCM?

    • Did we end up building any hardware? We have 10 or so
  • New hardware versions?

    • Lattice Nexus line board? Lattice previously seem interested in funding this?
    • Xilinx Artix Ultrascale?


  • AntMicro has all the HW it needs to do bring-up on the AC922.

    • Antmicro is going to attempt to replicate the Aussie results and then use these instructions as a start of the README
    • IBM did extend the loaner out another 60days
    • Update on bringup progress
      • Have the DC-SCM card installed, have microwatt running
      • No smoke
      • Can read/write GPIOs at stand-by
      • Have not yet been able to boot the system
    • Can Antmicro send a DC-SCM card to Toshaan so he can do some bringup
    • Todd would need to send the interposer from Rochester

OCP DC-SCM 2.0 Working Group -- Meets bi-weekly

  • Todd to run a call with Google and some other key players to discuss our common direction for the 3.0 standard. Still WIP. Trying to define the functions/areas that we need to go after. Lots of moving parts here in the industry.
    • Functions we are considering for 3.0
      • Full system design -- define the pin use cases specifically
      • Define a minimum connector size exploiting LTPI for most signals
        • MCU 8080. IDE bus protocol. Flexbus by Freescale. Industry Standard for 50yrs. XT/AT. ISA. PC104.
        • Consider looking at that
        • Asynch, interrupt driven
        • How many pins?
      • DCM-SCM hot plug definition
      • 1 to N DC-SCM to HPM
      • Out-band Redfish control / In-band WIP
      • Redundant Power pin definition
      • Consider multiple enet connectors

Conference Report follow ups

  • Nothing new yet. Working on setting up meetings with Microsoft and ASPEED near term.

Communication / Collaboration

  • Still seem to be issues with sending iCal meeting invites.

  • Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.




  • Renode looks like a good option for a simulation environment for LibreBMC.
    • Todd to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. WIP

Soft Cores

  • OPF is funding an FPGA optimized POWER soft core
    • Target was "VexRISCV" resource usage and performance. Todd to schedule a readout at a future meeting





FPGA Usage Barriers

  • List of opens (potential barriers) for using FPGAs as BMCs Update here?
    • Cost --
      • Projection is that will be cost competitive
      • Some things require an external chip
        • video driver, but could be added later
    • Soft Error Rates -- Munir to follow up
      • Hard fails roughly the same as an ASIC
      • Looks like Xilinx SER FIT is reasonable (<200).
      • And detectable and fixable with an image reload
      • Lattice to provide data on FIT rates and recovery design
    • Performance? 8X slower than an ASPEED?
      • Information from Lattice
        • much faster to BMC to boot. 2min for ASPEED. 5sec for FGPA
          • This is mostly a function of the BMC stack, the ASPEED vs FPGA, so potentially not Apples to Apples (ASPEED vs FPGA)
        • Lattice to provide some information on this performance comparisons to ASPEED
        • Opening up of LTPI is under consideration (MIT)
    • Image size

Project Ideas -- Running list of areas where we could use help

Workgroup Collaboration Tools

Community Involvement

  • Options for not needing an AC922

    • FPGA on both sides (emulating the HPM)
      • Raptor has such a board that has an FPGA on both sides
    • Can just use QEMU and simulate the AC922 side
  • How do we generate more activity/interest

    • Engage Universities -- There are interested universities

    • Todd to start a list of universities and contacts New direction here. Todd/Toshaan to make an OPF page "Education Page" that points to these projects as well as the OpenPOWER curriculum being developed. Then we can all point our education contacts to that page. No need to list them here

    • Need clear work breakdown. We have this for some projects.

    • Need Mentors. True for Interns/MLH/etc, but many projects can be supported in the open

    • Offer badges/certificates

    • Offer Bounties

    • Major League Hacking Interships

      • Start end of May.
      • Need to sign up by end of March
      • Must have sponsors to guide students and hold office hours
      • We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors
      • To use MLH, We need BoD (Board of Directors) approval
  • Need work items clearly identified and easily understood

    • Documentation -- We need build instructions, readmes, etc

      • Need someone replicate the FPGA/OpenBMC load from scratch
        • Then document the process for others to follow so they can replicate the results
          • Build all pieces -- Core, peripherals, OpenBMC,etc
        • Antmicro working this
    • Need official OpenBMC project and a makefile, bitbake/etc

    • Need the project broken down into manageable pieces

  • It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.

    • I did see an offer of help for a logo. I will follow up. TBD

Goals -- Need timelines on these -- WIP

  • Tasks defined and project broken down
  • Able to generate a bitstream for an FPGA using fully open source toolchain.
  • Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
  • Someone seriously starting to do a real (non-development) LibreBMC deployment.
  • Fully functional Gateware and OpenBMC code stack for AC922
  • Determine the performance/size

Next Meeting

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