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Meeting Minutes 2022-04-14 2022-04-14

LibreBMC SIG Meeting

Meeting date: 14 April 2022 Access link: Meeting ID: 91597478078

Call to Order

Anti-trust Reminder

This is a reminder that all OpenPOWER Foundation activities are subject to strict compliance with the OpenPOWER Foundations Antitrust Guidelines. Each individual participant and attendee at this meeting is responsible for knowing the contents of the Antitrust Guidelines, and for complying with the Antitrust Guidelines. Copies of the Antitrust Guidelines are available at: Antitrust Guidelines


New News

  • Anything new this week?

Hardware Update

  • Lattice ECP5 version of DC-SCM

    • Still missing some chips, but they do have the ECP5. Covid outbreak stopped chips.
  • Follow up on new hardware possabilities; From last meeting:


  • AntMicro has all the HW it needs to do bring-up on the AC922.

    • Todd sent a brief guide to Antmicro showing where the code is and steps taken by Mikey/co
    • Antmicro to attempt to replicate the results and then use these instructions as a start of the README
    • Update on this? Does AM have what they need?
      • Looks like AM has what they need on this

OCP DC-SCM 2.0 Working Group -- Meets bi-weekly

  • Todd to run a call with Google and some other key players to discuss our common direction for the 3.0 standard. Still WIP. Trying to define the functions/areas that we need to go after. Lots of moving parts here in the industry.

Conference Report follow ups

  • Nothing new yet. Working on setting up meetings with microsoft and ASPEED near term.

Communication / Collaboration

  • Still seem to be issues with sending iCal meeting invites.

    • Seems to add to the calendar, but puts in limited information
    • Update?
  • Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.




  • Renode looks like a good option for a simulation environment for LibreBMC.
    • Todd to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. WIP

Soft Cores

  • OPF is funding an FPGA optimized soft core
    • Target was "VexRISCV" resource usage and performance. Todd to schedule a readout at a future meeting




FPGA Usage Barriers

  • List of opens (potential barriers) for using FPGAs as BMCs Update here?
    • Cost -- Munir to follow up
    • Soft Error Rates -- Munir to follow up
      • Hard fails roughly the same as an ASIC
      • Looks like Xilinx SER FIT is reasonable (<200).
      • And detectable and fixable with an image reload
    • Performance? 8X slower than an ASPEED?
    • Image size
      • Todd to follow up with Munir from Lattice

Project Ideas -- Running list of areas where we could use help

Workgroup Collaboration Tools

Community Involvement

  • How do we generate more activity/interest

    • Engage Universities -- There are interested universities

    • Todd to start a list of universities and contacts

    • Need clear work breakdown

    • Need Mentors

    • Offer badges/certificates

    • Offer Bounties

    • Major League Hacking Interships

      • Start end of May.
      • Need to sign up by end of March
      • Must have sponsors to guide students and hold office hours
      • We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors
      • To use MLH, We need BoD (Board of Directors) approval
  • Need work items clearly identified and easily understood

    • Documentation -- We need build instructions, readmes, etc

      • Need someone replicate the FPGA/OpenBMC load from scratch
        • Then document the process for others to follow so they can replicate the results
          • Build all pieces -- Core, peripherals, OpenBMC,etc
        • Antmicro working this
    • Need official OpenBMC project and a makefile, bitbake/etc

    • Need the project broken down into manageable pieces

  • It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.

    • I did see an offer of help for a logo. I will follow up. TBD

Goals -- Need timelines on these -- WIP

  • Tasks defined and project broken down
  • Able to generate a bitstream for an FPGA using fully open source toolchain.
  • Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
  • Someone seriously starting to do a real (non-development) LibreBMC deployment.
  • Fully functional Gateware and OpenBMC code stack for AC922
  • Determine the performance/size

Next Meeting

{{< localdatetime date="2022-04-27" time="23:00" >}}