Add meeting minutes Apr 14 2022

Todd Rosedahl 1 year ago
parent cf7ca5b665
commit 2b0922b810

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title: Meeting Minutes 2022-04-14
date: 2022-04-14
- toddrosedahl,ibm
- toshaanbharvani,vantosh
- timansell,google
- karolgugala,antmicro
- lancealbertson,oregonstateuniversity
draft: false

# LibreBMC SIG Meeting

Meeting date: 14 April 2022
Access link:
Meeting ID: 91597478078

# Call to Order

### Anti-trust Reminder

This is a reminder that all OpenPOWER Foundation activities are subject to strict compliance with the OpenPOWER Foundations Antitrust Guidelines. Each individual participant and attendee at this meeting is responsible for knowing the contents of the Antitrust Guidelines, and for complying with the Antitrust Guidelines. Copies of the Antitrust Guidelines are available at: [Antitrust Guidelines](


## New News

* **Anything new this week?**

## Hardware Update

* Lattice ECP5 version of DC-SCM
* Still missing some chips, but they do have the ECP5. Covid outbreak stopped chips.

* Follow up on new hardware possabilities; **From last meeting:**
* Lattice [Crosslink NX]( or [Certus]( (from [Lattice's Nexus FPGAs]( based design -- Google funded open source tools here for a Google project.
* [Xilinx Artix Ultrascale+]( -- Would still need more work done with open source tooling, but [prjuray]( and [interchange format is starting]( to support these.
* **Could run at 400-500Mhz (vs 100Mhz)**
* [Xilinx Kintex 7 part]( is progressing pretty well. More like a $15-$20 USD cost part however...
* Antmicro are using a Kintex 7 in our [DataCenter RowHammer Tester board](
* Virtex support could be added but would need someone working on the open source tools to do this. More like >$50 USD cost part...

## Bringup

* AntMicro has all the HW it needs to do bring-up on the AC922.
* Todd sent a brief guide to Antmicro showing where the code is and steps taken by Mikey/co
* Antmicro to attempt to replicate the results and then use these instructions as a start of the README
* **Update on this? Does AM have what they need?**
* Looks like AM has what they need on this

## OCP DC-SCM 2.0 Working Group -- Meets bi-weekly

* **Todd** to run a call with Google and some other key players to discuss our common direction for the 3.0 standard. **Still WIP.** Trying to define the functions/areas that we need to go after. Lots of moving parts here in the industry.

## Conference Report follow ups

* Nothing new yet. **Working on setting up meetings with microsoft and ASPEED near term.**

## Communication / Collaboration

* Still seem to be issues with sending iCal meeting invites.
* Seems to add to the calendar, but puts in limited information
* **Update?**

* Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.

## Gateware


## Simulation

* Renode looks like a good option for a simulation environment for LibreBMC.
* **Todd** to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. **WIP**
## Soft Cores
* OPF is funding an FPGA optimized soft core
* Target was "VexRISCV" resource usage and performance. **Todd to schedule a readout at a future meeting**

## Toolchain

* **Items added by Tim last meeting. Left here to get the European audience**
* SymbiFlow is now called F4PGA (FOSS Flow For FPGA) and homed under the CHIPS Alliance;
* New website -
* Announcement -
* -
* (You might find the ["tools working group"]( and the ["SystemVerilog working group"](
* Xilinx is contributing to the f4pga-wg workgroup;
* There are also a lot of universities joining to participate.
* This is now gaining widespread support and adoption. SymbiFlow is becoming "real", not just for hobbiests

## Software


## FPGA Usage Barriers

* List of opens (potential barriers) for using FPGAs as BMCs **Update here?**
* Cost -- **Munir** to follow up
* Soft Error Rates -- **Munir** to follow up
* Hard fails roughly the same as an ASIC
* Looks like Xilinx SER FIT is reasonable (<200).
* And detectable and fixable with an image reload
* **Performance? 8X slower than an ASPEED?**
* Image size
* **Todd to follow up with Munir from Lattice**

## Project Ideas -- Running list of areas where we could use help

* **Near term project ideas -- things that could be worked on now**

* Linux-on-Litex-VexRiscV => Linux-on-Litex-Microwatt (/cc Anton)
* There is a demo showing linux running on VexRiscV
* Replicate this demo using Microwatt
* This can be now and questions asked/answered in the open
* Ask questions on github or on IRC #litex channel on Libera
* Add emulation of LPC peripheral to Renode (/cc Piotr)
* Questions asked/answered github
* Karol/Piotr can help as well directly
* Documentation (/cc all)
* Get a working litex configuration for microwatt
* microwatt is an option in litex, but it is not complete. Need the interrupt controller working and linux booting
* Need to just try booting linux, see what breaks,and fix it
* Joel Stanley would be a contact
* Add CI so we know when litex breaks
* See FPGA CI from Antmicro
* See work from Carl Karsten <> -
* **Could point students to Carl**
* See recent work from Enjoy Digital -
* We have an ecosystem of :micropython, u-boot, linux.
* All work, but only in specific configs. Documenting and testing those configurations would be a good project.
* Could use Zephyr
* Define a boot loader for microwatt
* Make it work across configurations (arty, orangecrab)
* Add Full OpenBMC support for the AC922
* Fork the Witherspoon OpenBMC and run it -- see what breaks

* Add Full Litex FPGA support (I2C, FSI, etc) More than just bit banging:
* Tim did this in the past -->
a. PCIe -
b. I2C/I3C -
c. USB -
d. FSI (uses I3C)
e. GPIOs -
f. LPC -- We have the gateware, but need integration with Litex
g. Ethernet -
h. Refclock
j. JTAG -
k. DDR -
l. SPI -

* **Mid-term ideas -- things that need more definition**

* Include the firmware into the CI infrastructure
* Need LiteX-Hub support and integration
* Add more FPGA boards supports
* Get it running on Raspbery PI
* Linux on LiteX VexRISCV like repository
* An example for just running a POWER Linux system on as many FPGA development boards as possible?
* -- >30 boards supported...
* Repository exists -

* Improving Ethernet performance.

* **Further Project Ideas from Tim:**
* It would be great to get help with getting GHDL into conda-eda
* It would be great to get help with adding POWER support into conda-eda
* It would be great to investigate "EDA Containers" for usage with LiteX

## Workgroup Collaboration Tools

* [Meeting Minutes](
* Meeting invites are still not seeming to get mailed?
* Long term TODO : Need to make the system actually sends emails with ical attachments. It will take awhile to make this work. Rather we should have interested parties import the cal and get notifications.
* [WebSys Document](

- OPF Discuss (with calendar and link to chat)

- Slack / IRC / Mattermost
#librebmc on libera (namespace)

- OPF Files

- OPF Discuss

- OPF GIT repository
Will be mirrored to github and gitlab

- OPF Kanban (linked with chat)

## Community Involvement

* How do we generate more activity/interest
* Engage Universities -- **There are interested universities**
* **Todd to start a list of universities and contacts**
* **Need clear work breakdown**
* **Need Mentors**

* Offer badges/certificates
* Offer Bounties
* Major League Hacking Interships
* Start end of May.
* Need to sign up by end of March
* Must have sponsors to guide students and hold office hours
* **We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors**
* To use MLH, We need BoD (Board of Directors) approval
* **Need work items clearly identified and easily understood**
* Documentation -- We need build instructions, readmes, etc
* Need someone replicate the FPGA/OpenBMC load from scratch
* Then document the process for others to follow so they can replicate the results
* Build all pieces -- Core, peripherals, OpenBMC,etc
* **Antmicro working this**

* Need official OpenBMC project and a makefile, bitbake/etc

* Need the project broken down into manageable pieces

* It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.
* **I did see an offer of help for a logo. I will follow up. TBD**

## Goals -- Need timelines on these -- WIP
* Tasks defined and project broken down
* Able to generate a bitstream for an FPGA using fully open source toolchain.
* Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
* Someone seriously starting to do a real (non-development) LibreBMC deployment.
* Fully functional Gateware and OpenBMC code stack for AC922
* Determine the performance/size

## Next Meeting

{{< localdatetime date="2022-04-27" time="23:00" >}}