amaranth conversion from nmigen

nmigen is now called amaranth so make the change here.

Other than the github URLS. This is just `sed -e s/nmigen/amaranth/g'

Signed-off-by: Michael Neuling <mikey@neuling.org>

.github/workflows/test.yml

@@ -12,14 +12,14 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v2
-      - run: pip3 install 'git+https://github.com/nmigen/nmigen.git'
-      - run: pip3 install 'git+https://github.com/nmigen/nmigen-soc.git'
+      - run: pip3 install 'git+https://github.com/amaranth-lang/amaranth.git'
+      - run: pip3 install 'git+https://github.com/amaranth-lang/amaranth-soc.git'
       - run: python -m unittest -v
 
   Verilog:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v2
-      - run: pip install git+https://github.com/nmigen/nmigen.git#egg=nmigen[builtin-yosys]
-      - run: pip3 install 'git+https://github.com/nmigen/nmigen-soc.git'
+      - run: pip install git+https://github.com/amaranth-lang/amaranth.git#egg=amaranth[builtin-yosys]
+      - run: pip3 install 'git+https://github.com/amaranth-lang/amaranth-soc.git'
       - run: python -m lpcperipheral.lpcperipheral

README.md

@@ -50,8 +50,8 @@ The LPC front end runs using the LPC clock. The rest of the design
 works on the normal system clock. Async FIFOs provide a safe boundary
 between the two.
 
-HDL is written in nmigen because that's what all the cool kids are
-doing. This is our first nmigen project, and we are software
+HDL is written in amaranth because that's what all the cool kids are
+doing. This is our first amaranth project, and we are software
 developers, so be kind!
 
 # Building

lpcperipheral/io_space.py

@@ -1,8 +1,8 @@
-from nmigen import Elaboratable, Module, Signal
-from nmigen.back import verilog
-from nmigen_soc.wishbone import Decoder as WishboneDecoder
-from nmigen_soc.wishbone import Interface as WishboneInterface
-from nmigen_soc.memory import MemoryMap
+from amaranth import Elaboratable, Module, Signal
+from amaranth.back import verilog
+from amaranth_soc.wishbone import Decoder as WishboneDecoder
+from amaranth_soc.wishbone import Interface as WishboneInterface
+from amaranth_soc.memory import MemoryMap
 
 from .ipmi_bt import IPMI_BT
 from .vuart_joined import VUartJoined

lpcperipheral/ipmi_bt.py

@@ -1,10 +1,10 @@
 from enum import IntEnum, unique
 
-from nmigen import Signal, Elaboratable, Module, ResetInserter, Cat
-from nmigen_soc.wishbone import Interface as WishboneInterface
-from nmigen.lib.fifo import SyncFIFOBuffered
+from amaranth import Signal, Elaboratable, Module, ResetInserter, Cat
+from amaranth_soc.wishbone import Interface as WishboneInterface
+from amaranth.lib.fifo import SyncFIFOBuffered
 
-from nmigen.back import verilog
+from amaranth.back import verilog
 
 
 @unique

lpcperipheral/lpc2wb.py

@@ -33,11 +33,11 @@
 # the LPC.
 #
 
-from nmigen import Signal, Elaboratable, Module
-from nmigen import ClockSignal, Cat, DomainRenamer, ResetSignal, ResetInserter
-from nmigen.lib.fifo import AsyncFIFO
-from nmigen_soc.wishbone import Interface as WishboneInterface
-from nmigen.back import verilog
+from amaranth import Signal, Elaboratable, Module
+from amaranth import ClockSignal, Cat, DomainRenamer, ResetSignal, ResetInserter
+from amaranth.lib.fifo import AsyncFIFO
+from amaranth_soc.wishbone import Interface as WishboneInterface
+from amaranth.back import verilog
 
 from .lpcfront import lpcfront, LPCCycletype, LPC_FW_DATA_WIDTH, LPC_FW_ADDR_WIDTH, LPC_IO_DATA_WIDTH, LPC_IO_ADDR_WIDTH
 

lpcperipheral/lpc_ctrl.py

@@ -7,12 +7,12 @@
 # DMA access into another master wishbone bus. Base and mask registers
 # (accessible via an IO wishbone bus) configure this
 
-from nmigen import Elaboratable, Module, Signal
-from nmigen_soc.wishbone import Interface as WishboneInterface
-from nmigen_soc.csr import Multiplexer as CSRMultiplexer
-from nmigen_soc.csr import Element as CSRElement
-from nmigen_soc.csr.wishbone import WishboneCSRBridge
-from nmigen.back import verilog
+from amaranth import Elaboratable, Module, Signal
+from amaranth_soc.wishbone import Interface as WishboneInterface
+from amaranth_soc.csr import Multiplexer as CSRMultiplexer
+from amaranth_soc.csr import Element as CSRElement
+from amaranth_soc.csr.wishbone import WishboneCSRBridge
+from amaranth.back import verilog
 
 
 class LPC_Ctrl(Elaboratable):

lpcperipheral/lpcfront.py

@@ -23,8 +23,8 @@
 #
 
 from enum import Enum, unique
-from nmigen import Signal, Elaboratable, Module, unsigned, Cat
-from nmigen.back import verilog
+from amaranth import Signal, Elaboratable, Module, unsigned, Cat
+from amaranth.back import verilog
 import math
 
 @unique

lpcperipheral/lpcperipheral.py

@@ -1,7 +1,7 @@
 from enum import Enum, unique
 
-from nmigen import Signal, Elaboratable, Module, Cat
-from nmigen.back import verilog
+from amaranth import Signal, Elaboratable, Module, Cat
+from amaranth.back import verilog
 
 from .io_space import IOSpace
 from .lpc2wb import lpc2wb

lpcperipheral/vuart.py

@@ -1,8 +1,8 @@
 from enum import Enum, unique
 
-from nmigen import Signal, Elaboratable, Module
-from nmigen_soc.wishbone import Interface as WishboneInterface
-from nmigen.back import verilog
+from amaranth import Signal, Elaboratable, Module
+from amaranth_soc.wishbone import Interface as WishboneInterface
+from amaranth.back import verilog
 
 
 @unique

lpcperipheral/vuart_joined.py

@@ -1,7 +1,7 @@
-from nmigen import Signal, Elaboratable, Module
-from nmigen.back import verilog
-from nmigen.lib.fifo import SyncFIFOBuffered
-from nmigen_soc.wishbone import Interface as WishboneInterface
+from amaranth import Signal, Elaboratable, Module
+from amaranth.back import verilog
+from amaranth.lib.fifo import SyncFIFOBuffered
+from amaranth_soc.wishbone import Interface as WishboneInterface
 
 from .vuart import VUart
 

setup.cfg

@@ -6,7 +6,7 @@ author_email = mikey@neuling.org, anton@ozlabs.org
 description = A simple LPC peripheral, with IPMI BT, Virtual UART and FW DMA
 long_description = file: README.md
 long_description_content_type = text/markdown
-keywords = nmigen
+keywords = amaranth
 platform = any
 license_file = LICENSE
 url = https://github.com/OpenPOWERFoundation/lpcperipheral

tests/ROM.py

@@ -1,7 +1,7 @@
 import math
-from nmigen import Elaboratable, Module, Memory
-from nmigen_soc.wishbone import Interface
-from nmigen.back import verilog
+from amaranth import Elaboratable, Module, Memory
+from amaranth_soc.wishbone import Interface
+from amaranth.back import verilog
 
 
 class ROM(Elaboratable, Interface):

tests/clocks.py

@@ -3,7 +3,7 @@
 # This is a little test program so I could work out how multiple clock
 # domains work. Not really part of this project but a handy refrence
 
-from nmigen import *
+from amaranth import *
 from enum import Enum, unique
 
 class clocks(Elaboratable):
@@ -29,7 +29,7 @@ class clocks(Elaboratable):
         return m
 
 # --- TEST ---
-from nmigen.sim import Simulator
+from amaranth.sim import Simulator
 
 
 dut = clocks()

tests/test_io_space.py

@@ -1,6 +1,6 @@
 import unittest
 
-from nmigen.sim import Simulator
+from amaranth.sim import Simulator
 
 from lpcperipheral.io_space import IOSpace
 from lpcperipheral.ipmi_bt import RegEnum, BMCRegEnum

tests/test_ipmi_bt.py

@@ -1,6 +1,6 @@
 import unittest
 
-from nmigen.sim import Simulator
+from amaranth.sim import Simulator
 
 from lpcperipheral.ipmi_bt import IPMI_BT, RegEnum, BMCRegEnum
 

tests/test_lpc.py

@@ -1,8 +1,8 @@
 import unittest
 
-from nmigen import Elaboratable, Module, Signal
-from nmigen_soc.wishbone import Interface as WishboneInterface
-from nmigen.sim import Simulator
+from amaranth import Elaboratable, Module, Signal
+from amaranth_soc.wishbone import Interface as WishboneInterface
+from amaranth.sim import Simulator
 
 from lpcperipheral.lpcperipheral import LPCPeripheral
 

tests/test_lpc2wb.py

@@ -1,7 +1,7 @@
 import unittest
 import random
 
-from nmigen.sim import Simulator
+from amaranth.sim import Simulator
 
 from lpcperipheral.lpc2wb import lpc2wb
 

tests/test_lpc_ctrl.py

@@ -1,8 +1,8 @@
 import unittest
 
-from nmigen import Elaboratable, Module
-from nmigen_soc.wishbone import Interface as WishboneInterface
-from nmigen.sim import Simulator
+from amaranth import Elaboratable, Module
+from amaranth_soc.wishbone import Interface as WishboneInterface
+from amaranth.sim import Simulator
 
 from lpcperipheral.lpc_ctrl import LPC_Ctrl
 

tests/test_vuart.py

@@ -1,6 +1,6 @@
 import unittest
 
-from nmigen.sim import Simulator
+from amaranth.sim import Simulator
 
 from lpcperipheral.vuart import VUart, RegEnum, LCR_DLAB
 from .helpers import Helpers

tests/test_vuart_joined.py

@@ -1,6 +1,6 @@
 import unittest
 
-from nmigen.sim import Simulator
+from amaranth.sim import Simulator
 
 from lpcperipheral.vuart import RegEnum
 from lpcperipheral.vuart_joined import VUartJoined