From 3f02b6e6e738309533b146999996c5e829e62a95 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 3 Feb 2022 12:44:49 +1100 Subject: [PATCH] amaranth conversion from nmigen nmigen is now called amaranth so make the change here. Other than the github URLS. This is just `sed -e s/nmigen/amaranth/g' Signed-off-by: Michael Neuling --- .github/workflows/test.yml | 8 ++++---- README.md | 4 ++-- lpcperipheral/io_space.py | 10 +++++----- lpcperipheral/ipmi_bt.py | 8 ++++---- lpcperipheral/lpc2wb.py | 10 +++++----- lpcperipheral/lpc_ctrl.py | 12 ++++++------ lpcperipheral/lpcfront.py | 4 ++-- lpcperipheral/lpcperipheral.py | 4 ++-- lpcperipheral/vuart.py | 6 +++--- lpcperipheral/vuart_joined.py | 8 ++++---- setup.cfg | 2 +- tests/ROM.py | 6 +++--- tests/clocks.py | 4 ++-- tests/test_io_space.py | 2 +- tests/test_ipmi_bt.py | 2 +- tests/test_lpc.py | 6 +++--- tests/test_lpc2wb.py | 2 +- tests/test_lpc_ctrl.py | 6 +++--- tests/test_vuart.py | 2 +- tests/test_vuart_joined.py | 2 +- 20 files changed, 54 insertions(+), 54 deletions(-) mode change 100755 => 100644 tests/clocks.py diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 3913766..900ec7b 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -12,14 +12,14 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - - run: pip3 install 'git+https://github.com/nmigen/nmigen.git' - - run: pip3 install 'git+https://github.com/nmigen/nmigen-soc.git' + - run: pip3 install 'git+https://github.com/amaranth-lang/amaranth.git' + - run: pip3 install 'git+https://github.com/amaranth-lang/amaranth-soc.git' - run: python -m unittest -v Verilog: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - - run: pip install git+https://github.com/nmigen/nmigen.git#egg=nmigen[builtin-yosys] - - run: pip3 install 'git+https://github.com/nmigen/nmigen-soc.git' + - run: pip install git+https://github.com/amaranth-lang/amaranth.git#egg=amaranth[builtin-yosys] + - run: pip3 install 'git+https://github.com/amaranth-lang/amaranth-soc.git' - run: python -m lpcperipheral.lpcperipheral \ No newline at end of file diff --git a/README.md b/README.md index e2eef6e..77458dc 100644 --- a/README.md +++ b/README.md @@ -50,8 +50,8 @@ The LPC front end runs using the LPC clock. The rest of the design works on the normal system clock. Async FIFOs provide a safe boundary between the two. -HDL is written in nmigen because that's what all the cool kids are -doing. This is our first nmigen project, and we are software +HDL is written in amaranth because that's what all the cool kids are +doing. This is our first amaranth project, and we are software developers, so be kind! # Building diff --git a/lpcperipheral/io_space.py b/lpcperipheral/io_space.py index 56b2778..660c89e 100644 --- a/lpcperipheral/io_space.py +++ b/lpcperipheral/io_space.py @@ -1,8 +1,8 @@ -from nmigen import Elaboratable, Module, Signal -from nmigen.back import verilog -from nmigen_soc.wishbone import Decoder as WishboneDecoder -from nmigen_soc.wishbone import Interface as WishboneInterface -from nmigen_soc.memory import MemoryMap +from amaranth import Elaboratable, Module, Signal +from amaranth.back import verilog +from amaranth_soc.wishbone import Decoder as WishboneDecoder +from amaranth_soc.wishbone import Interface as WishboneInterface +from amaranth_soc.memory import MemoryMap from .ipmi_bt import IPMI_BT from .vuart_joined import VUartJoined diff --git a/lpcperipheral/ipmi_bt.py b/lpcperipheral/ipmi_bt.py index c374852..8a24095 100644 --- a/lpcperipheral/ipmi_bt.py +++ b/lpcperipheral/ipmi_bt.py @@ -1,10 +1,10 @@ from enum import IntEnum, unique -from nmigen import Signal, Elaboratable, Module, ResetInserter, Cat -from nmigen_soc.wishbone import Interface as WishboneInterface -from nmigen.lib.fifo import SyncFIFOBuffered +from amaranth import Signal, Elaboratable, Module, ResetInserter, Cat +from amaranth_soc.wishbone import Interface as WishboneInterface +from amaranth.lib.fifo import SyncFIFOBuffered -from nmigen.back import verilog +from amaranth.back import verilog @unique diff --git a/lpcperipheral/lpc2wb.py b/lpcperipheral/lpc2wb.py index 6594966..effed3b 100644 --- a/lpcperipheral/lpc2wb.py +++ b/lpcperipheral/lpc2wb.py @@ -33,11 +33,11 @@ # the LPC. # -from nmigen import Signal, Elaboratable, Module -from nmigen import ClockSignal, Cat, DomainRenamer, ResetSignal, ResetInserter -from nmigen.lib.fifo import AsyncFIFO -from nmigen_soc.wishbone import Interface as WishboneInterface -from nmigen.back import verilog +from amaranth import Signal, Elaboratable, Module +from amaranth import ClockSignal, Cat, DomainRenamer, ResetSignal, ResetInserter +from amaranth.lib.fifo import AsyncFIFO +from amaranth_soc.wishbone import Interface as WishboneInterface +from amaranth.back import verilog from .lpcfront import lpcfront, LPCCycletype, LPC_FW_DATA_WIDTH, LPC_FW_ADDR_WIDTH, LPC_IO_DATA_WIDTH, LPC_IO_ADDR_WIDTH diff --git a/lpcperipheral/lpc_ctrl.py b/lpcperipheral/lpc_ctrl.py index 0411eb2..778de0e 100644 --- a/lpcperipheral/lpc_ctrl.py +++ b/lpcperipheral/lpc_ctrl.py @@ -7,12 +7,12 @@ # DMA access into another master wishbone bus. Base and mask registers # (accessible via an IO wishbone bus) configure this -from nmigen import Elaboratable, Module, Signal -from nmigen_soc.wishbone import Interface as WishboneInterface -from nmigen_soc.csr import Multiplexer as CSRMultiplexer -from nmigen_soc.csr import Element as CSRElement -from nmigen_soc.csr.wishbone import WishboneCSRBridge -from nmigen.back import verilog +from amaranth import Elaboratable, Module, Signal +from amaranth_soc.wishbone import Interface as WishboneInterface +from amaranth_soc.csr import Multiplexer as CSRMultiplexer +from amaranth_soc.csr import Element as CSRElement +from amaranth_soc.csr.wishbone import WishboneCSRBridge +from amaranth.back import verilog class LPC_Ctrl(Elaboratable): diff --git a/lpcperipheral/lpcfront.py b/lpcperipheral/lpcfront.py index 50a258a..3b6c02d 100644 --- a/lpcperipheral/lpcfront.py +++ b/lpcperipheral/lpcfront.py @@ -23,8 +23,8 @@ # from enum import Enum, unique -from nmigen import Signal, Elaboratable, Module, unsigned, Cat -from nmigen.back import verilog +from amaranth import Signal, Elaboratable, Module, unsigned, Cat +from amaranth.back import verilog import math @unique diff --git a/lpcperipheral/lpcperipheral.py b/lpcperipheral/lpcperipheral.py index e2cb028..7dfda39 100644 --- a/lpcperipheral/lpcperipheral.py +++ b/lpcperipheral/lpcperipheral.py @@ -1,7 +1,7 @@ from enum import Enum, unique -from nmigen import Signal, Elaboratable, Module, Cat -from nmigen.back import verilog +from amaranth import Signal, Elaboratable, Module, Cat +from amaranth.back import verilog from .io_space import IOSpace from .lpc2wb import lpc2wb diff --git a/lpcperipheral/vuart.py b/lpcperipheral/vuart.py index d873493..5cadd7b 100644 --- a/lpcperipheral/vuart.py +++ b/lpcperipheral/vuart.py @@ -1,8 +1,8 @@ from enum import Enum, unique -from nmigen import Signal, Elaboratable, Module -from nmigen_soc.wishbone import Interface as WishboneInterface -from nmigen.back import verilog +from amaranth import Signal, Elaboratable, Module +from amaranth_soc.wishbone import Interface as WishboneInterface +from amaranth.back import verilog @unique diff --git a/lpcperipheral/vuart_joined.py b/lpcperipheral/vuart_joined.py index a9648e6..c23ae7a 100644 --- a/lpcperipheral/vuart_joined.py +++ b/lpcperipheral/vuart_joined.py @@ -1,7 +1,7 @@ -from nmigen import Signal, Elaboratable, Module -from nmigen.back import verilog -from nmigen.lib.fifo import SyncFIFOBuffered -from nmigen_soc.wishbone import Interface as WishboneInterface +from amaranth import Signal, Elaboratable, Module +from amaranth.back import verilog +from amaranth.lib.fifo import SyncFIFOBuffered +from amaranth_soc.wishbone import Interface as WishboneInterface from .vuart import VUart diff --git a/setup.cfg b/setup.cfg index 32b277c..d45b4cb 100644 --- a/setup.cfg +++ b/setup.cfg @@ -6,7 +6,7 @@ author_email = mikey@neuling.org, anton@ozlabs.org description = A simple LPC peripheral, with IPMI BT, Virtual UART and FW DMA long_description = file: README.md long_description_content_type = text/markdown -keywords = nmigen +keywords = amaranth platform = any license_file = LICENSE url = https://github.com/OpenPOWERFoundation/lpcperipheral diff --git a/tests/ROM.py b/tests/ROM.py index cffeeb8..08b96e4 100644 --- a/tests/ROM.py +++ b/tests/ROM.py @@ -1,7 +1,7 @@ import math -from nmigen import Elaboratable, Module, Memory -from nmigen_soc.wishbone import Interface -from nmigen.back import verilog +from amaranth import Elaboratable, Module, Memory +from amaranth_soc.wishbone import Interface +from amaranth.back import verilog class ROM(Elaboratable, Interface): diff --git a/tests/clocks.py b/tests/clocks.py old mode 100755 new mode 100644 index 1bdb7c8..943602a --- a/tests/clocks.py +++ b/tests/clocks.py @@ -3,7 +3,7 @@ # This is a little test program so I could work out how multiple clock # domains work. Not really part of this project but a handy refrence -from nmigen import * +from amaranth import * from enum import Enum, unique class clocks(Elaboratable): @@ -29,7 +29,7 @@ class clocks(Elaboratable): return m # --- TEST --- -from nmigen.sim import Simulator +from amaranth.sim import Simulator dut = clocks() diff --git a/tests/test_io_space.py b/tests/test_io_space.py index 425b4c2..0c34f71 100644 --- a/tests/test_io_space.py +++ b/tests/test_io_space.py @@ -1,6 +1,6 @@ import unittest -from nmigen.sim import Simulator +from amaranth.sim import Simulator from lpcperipheral.io_space import IOSpace from lpcperipheral.ipmi_bt import RegEnum, BMCRegEnum diff --git a/tests/test_ipmi_bt.py b/tests/test_ipmi_bt.py index 0536646..f655078 100644 --- a/tests/test_ipmi_bt.py +++ b/tests/test_ipmi_bt.py @@ -1,6 +1,6 @@ import unittest -from nmigen.sim import Simulator +from amaranth.sim import Simulator from lpcperipheral.ipmi_bt import IPMI_BT, RegEnum, BMCRegEnum diff --git a/tests/test_lpc.py b/tests/test_lpc.py index 0b11a7d..f74b095 100644 --- a/tests/test_lpc.py +++ b/tests/test_lpc.py @@ -1,8 +1,8 @@ import unittest -from nmigen import Elaboratable, Module, Signal -from nmigen_soc.wishbone import Interface as WishboneInterface -from nmigen.sim import Simulator +from amaranth import Elaboratable, Module, Signal +from amaranth_soc.wishbone import Interface as WishboneInterface +from amaranth.sim import Simulator from lpcperipheral.lpcperipheral import LPCPeripheral diff --git a/tests/test_lpc2wb.py b/tests/test_lpc2wb.py index a5a8c16..1ad4214 100644 --- a/tests/test_lpc2wb.py +++ b/tests/test_lpc2wb.py @@ -1,7 +1,7 @@ import unittest import random -from nmigen.sim import Simulator +from amaranth.sim import Simulator from lpcperipheral.lpc2wb import lpc2wb diff --git a/tests/test_lpc_ctrl.py b/tests/test_lpc_ctrl.py index 31078f5..8da3bda 100644 --- a/tests/test_lpc_ctrl.py +++ b/tests/test_lpc_ctrl.py @@ -1,8 +1,8 @@ import unittest -from nmigen import Elaboratable, Module -from nmigen_soc.wishbone import Interface as WishboneInterface -from nmigen.sim import Simulator +from amaranth import Elaboratable, Module +from amaranth_soc.wishbone import Interface as WishboneInterface +from amaranth.sim import Simulator from lpcperipheral.lpc_ctrl import LPC_Ctrl diff --git a/tests/test_vuart.py b/tests/test_vuart.py index 04dd2da..71b4534 100644 --- a/tests/test_vuart.py +++ b/tests/test_vuart.py @@ -1,6 +1,6 @@ import unittest -from nmigen.sim import Simulator +from amaranth.sim import Simulator from lpcperipheral.vuart import VUart, RegEnum, LCR_DLAB from .helpers import Helpers diff --git a/tests/test_vuart_joined.py b/tests/test_vuart_joined.py index 615eaa4..d379514 100644 --- a/tests/test_vuart_joined.py +++ b/tests/test_vuart_joined.py @@ -1,6 +1,6 @@ import unittest -from nmigen.sim import Simulator +from amaranth.sim import Simulator from lpcperipheral.vuart import RegEnum from lpcperipheral.vuart_joined import VUartJoined