librebmc
/
ac922interposer
34
1
Fork 0
Code Issues 2 Pull Requests Projects Releases 1 Wiki Activity

Removed extra junctions that were shorting 2.5v to gnd.

Browse Source
main
Steven Roberts 4 years ago
parent 98202d3aa3
commit 5d9d922aca
3 changed files with 2212 additions and 41 deletions
Show Stats Download Patch File Download Diff File

29
SequoiaConnector.sch
Unescape Escape View File

@ -265,7 +265,7 @@ Wire Wire Line
8000 1950 8000 2050 8000 1950 8000 2050
Wire Wire Line Wire Wire Line
8000 2350 8000 2500 8000 2350 8000 2500
Text Label 7250 2050 0 50 ~ 0 Text Label 7300 2050 0 50 ~ 0
12VCS_RESET_N 12VCS_RESET_N
Text GLabel 4250 6150 2 50 Input ~ 0 Text GLabel 4250 6150 2 50 Input ~ 0
+3.3VCS +3.3VCS
@ -476,8 +476,6 @@ Wire Wire Line
Connection ~ 3600 7150 Connection ~ 3600 7150
Wire Wire Line Wire Wire Line
7050 1750 7700 1750 7050 1750 7700 1750
Wire Wire Line
7050 2050 7250 2050
Text GLabel 7600 5450 2 50 BiDi ~ 0 Text GLabel 7600 5450 2 50 BiDi ~ 0
ESPI_IO1 ESPI_IO1
Wire Wire Line Wire Wire Line
@ -516,8 +514,6 @@ Wire Wire Line
8800 3750 9000 3750 8800 3750 9000 3750
Wire Wire Line Wire Wire Line
9000 3750 9000 3450 9000 3750 9000 3450
Wire Wire Line
7050 5550 7250 5550
$Comp $Comp
L power:GND #PWR023 L power:GND #PWR023
U 1 1 632AB254 U 1 1 632AB254
@ -710,8 +706,6 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
7050 3950 7300 3950 7050 3950 7300 3950
Connection ~ 7300 3950 Connection ~ 7300 3950
Wire Wire Line
7250 2150 7250 2050
Connection ~ 7250 2150 Connection ~ 7250 2150
Wire Wire Line Wire Wire Line
7050 2150 7250 2150 7050 2150 7250 2150
@ -740,11 +734,6 @@ F 3 "" H 7250 2400 50 0001 C CNN
$EndComp $EndComp
Wire Wire Line Wire Wire Line
7250 2150 7250 2400 7250 2150 7250 2400
Connection ~ 7250 2050
Wire Wire Line
7250 2050 8000 2050
Wire Wire Line
7250 2050 7250 1850
Text GLabel 5750 6750 2 50 Input ~ 0 Text GLabel 5750 6750 2 50 Input ~ 0
I3C3_SCL I3C3_SCL
Text GLabel 5750 7050 2 50 BiDi ~ 0 Text GLabel 5750 7050 2 50 BiDi ~ 0
@ -826,9 +815,6 @@ Wire Wire Line
Connection ~ 7250 5350 Connection ~ 7250 5350
Wire Wire Line Wire Wire Line
7250 5350 7250 5050 7250 5350 7250 5050
Connection ~ 7250 5550
Wire Wire Line
7250 5550 7600 5550
Wire Wire Line Wire Wire Line
10550 1250 10350 1250 10550 1250 10350 1250
Wire Wire Line Wire Wire Line
@ -1133,13 +1119,8 @@ Text GLabel 1800 5450 2 50 Output ~ 0
+2.5VCS +2.5VCS
Wire Wire Line Wire Wire Line
1500 5450 1750 5450 1500 5450 1750 5450
Wire Wire Line
1500 5550 1700 5550
Wire Wire Line Wire Wire Line
1750 5550 1750 5450 1750 5550 1750 5450
Connection ~ 1700 5550
Wire Wire Line
1700 5550 1750 5550
Connection ~ 1750 5450 Connection ~ 1750 5450
Wire Wire Line Wire Wire Line
1750 5450 1800 5450 1750 5450 1800 5450
@ -1147,4 +1128,12 @@ Wire Wire Line
3650 4550 3300 4550 3650 4550 3300 4550
Wire Wire Line Wire Wire Line
3650 4650 3300 4650 3650 4650 3300 4650
Wire Wire Line
1500 5550 1750 5550
Wire Wire Line
7050 5550 7600 5550
Wire Wire Line
7050 2050 8000 2050
Wire Wire Line
7250 1850 7250 2150
$EndSCHEMATC $EndSCHEMATC

1979
ac922interposer.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

245
ac922interposer.pro
Unescape Escape View File

@ -1,29 +1,10 @@
update=Mon 12 Apr 2021 02:20:37 PM CDT update=Fri 16 Apr 2021 04:21:28 PM CDT
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
version=1 version=1
RootSch= RootSch=
BoardNm= BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb] [cvpcb]
version=1 version=1
NetIExt=net NetIExt=net
@ -41,3 +22,227 @@ NetFmtName=Pcbnew
SpiceAjustPassiveValues=0 SpiceAjustPassiveValues=0
LabSize=50 LabSize=50
ERC_TestSimilarLabels=1 ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=ac922interposer.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=1
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

Write Preview
Loading…
Cancel
Save