# //  Questa Sim-64
# //  Version 2020.3_1 linux_x86_64 Aug 25 2020
# //
# //  Copyright 1991-2020 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
pwd
# /home/ptikals/IBM/osu-toy-sram/src
do top.do
# Cannot open macro file: top.do
cd ../sim
do top.do
# QuestaSim-64 vlog 2020.3_1 Compiler 2020.08 Aug 25 2020
# Start time: 11:20:19 on Dec 14,2021
# vlog -reportprogress 300 -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr.v ../src/ra_2r1w_64x72_sdr.v ../src/ra_cfg_ddr.v ../src/regfile_2r1w_64x24.v ../src/toysram.vh ../src/ra_4r2w_64x72_ddr_1x.v ../src/ra_cfg_sdr.v ../src/regfile_4r2w_64x24.v ../src/ra_4r2w_64x72_ddr.v ../src/ra_delay.v ../src/ra_lcb_sdr.v ../src/ra_lcb_ddr.v ../src/test_ra_ddr.v ../src/test_ra_sdr.sv ../src/test_ra_ddr_1x.v 
# -- Compiling module address_clock_sdr_2r1w_64
# -- Compiling module ra_bist_ddr
# -- Compiling module predecode_sdr_64
# -- Compiling module ra_bist_sdr
# -- Compiling module ra_2r1w_64x72_sdr
# -- Compiling module ra_cfg_ddr
# -- Compiling module regfile_2r1w_64x24
# -- Compiling module ra_4r2w_64x72_ddr_1x
# -- Compiling module ra_cfg_sdr
# -- Compiling module regfile_4r2w_64x24
# -- Compiling module ra_4r2w_64x72_ddr
# -- Compiling module ra_delay
# -- Compiling module ra_lcb_sdr
# ** Warning: ../src/ra_lcb_sdr.v(61): (vlog-2623) Undefined variable: i.
# -- Compiling module ra_lcb_ddr
# -- Compiling module test_ra_ddr
# -- Compiling module test_ra_sdr
# ** Warning: ../src/test_ra_sdr.sv(28): (vlog-2605) empty port name in port list.
# -- Compiling module test_ra_ddr_1x
# 
# Top level modules:
# 	ra_bist_sdr
# 	test_ra_ddr
# 	test_ra_sdr
# 	test_ra_ddr_1x
# End time: 11:20:19 on Dec 14,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 2
# vsim -debugdb -voptargs="+acc" work.test_ra_sdr 
# Start time: 11:20:19 on Dec 14,2021
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-8611) Generating debug db.
# ** Error: ../src/test_ra_sdr.sv(85): Module 'ra_bist_sdr_osu' is not defined.
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0.
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./top.do PAUSED at line 33
do top.do
# QuestaSim-64 vlog 2020.3_1 Compiler 2020.08 Aug 25 2020
# Start time: 11:29:26 on Dec 14,2021
# vlog -reportprogress 300 -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../src/ra_cfg_ddr.v ../src/regfile_2r1w_64x24.v ../src/toysram.vh ../src/ra_4r2w_64x72_ddr_1x.v ../src/ra_cfg_sdr.v ../src/regfile_4r2w_64x24.v ../src/ra_4r2w_64x72_ddr.v ../src/ra_delay.v ../src/ra_lcb_sdr.v ../src/ra_lcb_ddr.v ../src/test_ra_ddr.v ../src/test_ra_sdr.sv ../src/test_ra_ddr_1x.v 
# -- Compiling module address_clock_sdr_2r1w_64
# -- Compiling module ra_bist_ddr
# -- Compiling module predecode_sdr_64
# -- Compiling module ra_bist_sdr
# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-2730) Undefined variable: 'int'.
# ** Error: (vlog-13069) ../src/ra_bist_sdr_osu.v(88): near "i": syntax error, unexpected IDENTIFIER, expecting '='.
# ** Error: (vlog-13036) ../src/ra_bist_sdr_osu.v(88): near "++": Operator only allowed in SystemVerilog.
# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-13205) Syntax error found in the scope following 'i'. Is there a missing '::'?
# -- Compiling module ra_2r1w_64x72_sdr
# -- Compiling module ra_cfg_ddr
# -- Compiling module regfile_2r1w_64x24
# -- Compiling module ra_4r2w_64x72_ddr_1x
# -- Compiling module ra_cfg_sdr
# -- Compiling module regfile_4r2w_64x24
# -- Compiling module ra_4r2w_64x72_ddr
# -- Compiling module ra_delay
# -- Compiling module ra_lcb_sdr
# ** Warning: ../src/ra_lcb_sdr.v(61): (vlog-2623) Undefined variable: i.
# -- Compiling module ra_lcb_ddr
# -- Compiling module test_ra_ddr
# -- Compiling module test_ra_sdr
# ** Warning: ../src/test_ra_sdr.sv(28): (vlog-2605) empty port name in port list.
# -- Compiling module test_ra_ddr_1x
# End time: 11:29:26 on Dec 14,2021, Elapsed time: 0:00:00
# Errors: 4, Warnings: 2
# ** Error: /opt/Mentor/questasim/linux_x86_64/vlog failed.
# Error in macro ./top.do line 30
# /opt/Mentor/questasim/linux_x86_64/vlog failed.
#     while executing
# "vlog -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../sr..."
do top.do
# QuestaSim-64 vlog 2020.3_1 Compiler 2020.08 Aug 25 2020
# Start time: 11:49:53 on Dec 14,2021
# vlog -reportprogress 300 -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../src/ra_cfg_ddr.v ../src/regfile_2r1w_64x24.v ../src/toysram.vh ../src/ra_4r2w_64x72_ddr_1x.v ../src/ra_cfg_sdr.v ../src/regfile_4r2w_64x24.v ../src/ra_4r2w_64x72_ddr.v ../src/ra_delay.v ../src/ra_lcb_sdr.v ../src/ra_lcb_ddr.v ../src/test_ra_ddr.v ../src/test_ra_sdr.sv ../src/test_ra_ddr_1x.v 
# -- Compiling module address_clock_sdr_2r1w_64
# -- Compiling module ra_bist_ddr
# -- Compiling module predecode_sdr_64
# -- Compiling module ra_bist_sdr
# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-2730) Undefined variable: 'int'.
# ** Error: (vlog-13069) ../src/ra_bist_sdr_osu.v(88): near "i": syntax error, unexpected IDENTIFIER, expecting '='.
# ** Error: ../src/ra_bist_sdr_osu.v(88): (vlog-13205) Syntax error found in the scope following 'i'. Is there a missing '::'?
# -- Compiling module ra_2r1w_64x72_sdr
# -- Compiling module ra_cfg_ddr
# -- Compiling module regfile_2r1w_64x24
# -- Compiling module ra_4r2w_64x72_ddr_1x
# -- Compiling module ra_cfg_sdr
# -- Compiling module regfile_4r2w_64x24
# -- Compiling module ra_4r2w_64x72_ddr
# -- Compiling module ra_delay
# -- Compiling module ra_lcb_sdr
# ** Warning: ../src/ra_lcb_sdr.v(61): (vlog-2623) Undefined variable: i.
# -- Compiling module ra_lcb_ddr
# -- Compiling module test_ra_ddr
# -- Compiling module test_ra_sdr
# ** Warning: ../src/test_ra_sdr.sv(28): (vlog-2605) empty port name in port list.
# -- Compiling module test_ra_ddr_1x
# End time: 11:49:53 on Dec 14,2021, Elapsed time: 0:00:00
# Errors: 3, Warnings: 2
# ** Error: /opt/Mentor/questasim/linux_x86_64/vlog failed.
# Error in macro ./top.do line 30
# /opt/Mentor/questasim/linux_x86_64/vlog failed.
#     while executing
# "vlog -lint ../src/address_clock_sdr_2r1w_64.v ../src/ra_bist_ddr.v ../src/predecode_sdr_64.v ../src/ra_bist_sdr_osu.v ../src/ra_2r1w_64x72_sdr.v ../sr..."
# End time: 12:39:15 on Dec 14,2021, Elapsed time: 1:18:56
# Errors: 3, Warnings: 0