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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Local Clock Buffer for arrays
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// Generates sim or implementation logic, depending on GENMODE.
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`timescale 1 ns / 1 ns
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`include "toysram.vh"
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module ra_lcb_sdr (
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clk,
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reset,
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cfg,
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strobe
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);
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parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
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input clk;
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input reset;
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input [0:`LCBSDR_CONFIGWIDTH-1] cfg;
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output strobe;
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wire clk_dly;
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wire i;
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wire o0;
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wire o1;
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wire clk_dly2;
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// generate strobe
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generate
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if (GENMODE == 0)
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assign strobe = !clk & !reset;
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else begin
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// generate a strobe for sdr
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// clk -> [delay] -> * --------------------- * -- and ---
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// | -- [delay] --- inv ---|
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// first edge delay
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ra_delay d0 (
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.i(i),
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.o(o0)
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);
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// remaining
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/*
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genvar i;
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for (i = 1; i < `MAX_PULSE_DELAYS-1; i = i + 1) begin : d1
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ra_delay (
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.i()
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.o()
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)
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end
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*/
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// select tap based on cfg
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assign clk_dly = o0;
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// first width delay
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ra_delay w0 (
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.i(clk_dly),
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.o(o1)
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);
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// remaining
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// select tap based on cfg
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assign clk_dly2 = o1;
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// create strobe
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assign strobe = clk_dly & !clk_dly2;
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end
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endgenerate
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endmodule
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