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toy-sram
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toy-sram/rtl
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openpowerwtf f46f717930 netlist sim.txt, .fst 2 years ago
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build init 2 years ago
sim netlist sim.txt, .fst 2 years ago
src 64x72 sim 2 years ago
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readme.md

Logical Array Wrapper

  • verilog is in rtl/src/array
  • parameter determines sim vs tech during rtl compile

Physical Array

  • custom cell(s) to be designed
  • custom/

Test Site

  • verilog is in rtl/src/site
  • supporting logic for test and debug through available Caravel connections

Verification

  • rtl/sim/coco

Caravel