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38 lines
1.4 KiB
Markdown
38 lines
1.4 KiB
Markdown
# Next Steps
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* LVS (Open source)
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- Extract SPICE file from 10T_32x32_magic.mag.
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- Extract SPICE file from 10T_32x32_xschem.sch.
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- Run the script: runlvs_single.sh (Might have to look at the script and
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figure out what files need to be where).
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- It will print a .out file.
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* Extract GDS file (Magic)
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- Pull up 10T_32x32_magic.mag in magic.
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- In the magic terminal type: "gds".
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- That extracts the GDS file.
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* Extract LEF file (NDA Flow)
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- There is a flow to do this in Abstract.
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- This needs all GDS files of layouts we want to use in synthesis and PnR.
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- Outputs a ".lef" file.
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* Liberty Characterization (NDA Flow)
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- This needs SPICE files of our layout (i.e. SRAM) and the SPICE
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files of the SKY130 models (i.e. sky130_fd_pr__.....)
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- This gives timing and power characteristics of the layout/cell.
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- Outputs a ".lib" file needed for synth and PnR.
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* Synthesis (NDA Flow)
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- We need the Verilog files for design we want to make.
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- We need the Liberty file for our standard cell library so that it can
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make a "gate level" netlist of the design.
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- Will give us timing and power metrics of the design using our cells.
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- This produces a lot of files.
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* Place and Route (NDA Flow)
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- This needs SPICE, LEF, GDS, LIB, Output from Synthesis.
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- This also outputs a bunch of files.
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- Our end goal is to have a GDS file of our placed and routed design.
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- "signoff.gds"
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