v0.02
Bill Flynn
10 months ago
committed by
GitHub
parent
2655d4db36
commit
14ab45a97f
@ -0,0 +1,76 @@
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Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
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Subcircuit pins:
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Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
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-------------------------------------------|-------------------------------------------
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1 |1
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2 |2
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3 |3
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4 |4
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
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Circuit 1 cell sky130_fd_pr__pfet_01v8 and Circuit 2 cell sky130_fd_pr__pfet_01v8 are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
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Subcircuit pins:
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Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8
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-------------------------------------------|-------------------------------------------
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1 |1
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2 |2
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3 |3
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4 |4
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent.
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Flattening unmatched subcell INVX1 in circuit 10T_toy_xschem (1)(2 instances)
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Subcircuit summary:
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Circuit 1: toysram_bit |Circuit 2: 10T_toy_xschem
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__nfet_01v8 (8) |sky130_fd_pr__nfet_01v8 (8)
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sky130_fd_pr__pfet_01v8 (2) |sky130_fd_pr__pfet_01v8 (2)
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Number of devices: 10 |Number of devices: 10
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Number of nets: 15 **Mismatch** |Number of nets: 13 **Mismatch**
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---------------------------------------------------------------------------------------
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NET mismatches: Class fragments follow (with fanout counts):
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Circuit 1: toysram_bit |Circuit 2: 10T_toy_xschem
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---------------------------------------------------------------------------------------
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Net: VDD |Net: GND
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sky130_fd_pr__pfet_01v8/(1|3) = 2 | sky130_fd_pr__nfet_01v8/(1|3) = 4
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| sky130_fd_pr__nfet_01v8/4 = 8
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Net: w_210_89# |(no matching net)
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sky130_fd_pr__pfet_01v8/4 = 2 |
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Net: VSUBS |(no matching net)
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sky130_fd_pr__nfet_01v8/4 = 8 |
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---------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------
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Net: WWL |Net: WWL
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sky130_fd_pr__nfet_01v8/2 = 2 | sky130_fd_pr__nfet_01v8/2 = 2
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---------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------
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Net: GND |Net: VDD
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sky130_fd_pr__nfet_01v8/(1|3) = 4 | sky130_fd_pr__pfet_01v8/(1|3) = 2
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| sky130_fd_pr__pfet_01v8/4 = 2
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---------------------------------------------------------------------------------------
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Netlists do not match.
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Subcircuit pins:
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Circuit 1: toysram_bit |Circuit 2: 10T_toy_xschem
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-------------------------------------------|-------------------------------------------
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VDD |(no matching pin)
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WWL |WWL
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Cell pin lists are equivalent.
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Device classes toysram_bit and 10T_toy_xschem are equivalent.
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Final result: Netlists do not match.
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@ -1 +1,17 @@
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# gdsfactory cell
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```
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# gen toysram_bit.gds
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bit_v0.02.py 4.75,2.5
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# extract
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magic -dnull -noconsole -rcfile magic_extract_bit.tcl toysram_bit.gds
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# irsim
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magic -rcfile magic_irsim_bit.tcl toysram_bit.gds&
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# lvs
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netgen -batch lvs "toysram_bit.spice toysram_bit" "../xschem/10T_toy_xschem.spice 10T_toy_xschem" sky130A_setup.tcl netgen.log
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# lef
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magic -rcfile magic.tcl toysram_bit.gds
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# console
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select
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lef write
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```
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@ -0,0 +1,111 @@
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timestamp 1400616048
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version 8.3
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tech sky130A
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style ngspice()
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scale 1000 1 500000
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resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
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parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
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parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
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port "RBL1" 10 718 29 752 63 m1
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port "RBL1" 10 644 12 644 12 m1
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port "WBLb" 8 480 29 514 63 m1
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port "WBLb" 8 364 12 364 12 m1
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port "RWL1" 14 899 80 933 114 m2
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port "GND" 5 718 241 752 275 m1
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port "GND" 5 420 224 420 224 m1
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port "VDD" 6 277 241 311 275 m1
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port "VDD" 6 210 224 210 224 m1
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port "inv1_q" 7 126 178 126 178 li
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port "inv2_q" 4 196 336 196 336 li
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port "RWL0" 12 899 396 933 430 m2
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port "RBL0" 9 718 449 752 483 m1
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port "RBL0" 9 644 432 644 432 m1
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port "WWL" 2 39 405 73 439 m2
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port "WWL" 2 0 388 0 388 m2
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port "WBL" 3 480 449 514 483 m1
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port "WBL" 3 392 432 392 432 m1
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node "RBL1" 212 80.6165 644 12 m1 0 0 0 0 0 0 0 0 9576 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 12376 500 0 0 0 0 0 0 0 0 0 0
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node "WBLb" 160 94.0802 364 12 m1 0 0 0 0 0 0 0 0 7840 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 13328 528 0 0 0 0 0 0 0 0 0 0
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node "RWL1" 482 253.755 899 80 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11704 744 0 0 4624 272 4624 272 4624 272 0 0 0 0 0 0 0 0
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node "a_672_110#" 180 0 672 110 ndif 0 0 0 0 0 0 0 0 10584 420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "GND" 838 105.064 420 224 m1 0 0 0 0 0 0 0 0 15232 720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9248 544 36040 1196 0 0 0 0 0 0 0 0 0 0
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node "VDD" 256 68.4255 210 224 m1 0 0 0 0 0 0 0 0 0 0 5712 304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 11424 472 0 0 0 0 0 0 0 0 0 0
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node "a_672_322#" 204 0 672 322 ndif 0 0 0 0 0 0 0 0 9324 400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "inv1_q" 1773 355.959 126 178 li 0 0 0 0 0 0 0 0 8232 364 5460 298 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24544 1600 0 0 22202 1306 0 0 0 0 0 0 0 0 0 0 0 0
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node "inv2_q" 1738 325.188 196 336 li 0 0 0 0 0 0 0 0 7252 344 4956 286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23104 1504 0 0 21998 1294 0 0 0 0 0 0 0 0 0 0 0 0
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node "RWL0" 482 253.271 899 396 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11704 744 0 0 4624 272 4624 272 4624 272 0 0 0 0 0 0 0 0
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node "RBL0" 207 81.5513 644 432 m1 0 0 0 0 0 0 0 0 9828 408 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 12376 500 0 0 0 0 0 0 0 0 0 0
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node "WWL" 1908 793.37 0 388 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38168 2472 0 0 9248 544 9248 544 28560 976 0 0 0 0 0 0 0 0
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node "WBL" 172 80.8495 392 432 m1 0 0 0 0 0 0 0 0 7252 344 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 11424 472 0 0 0 0 0 0 0 0 0 0
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node "w_210_89#" 1877 167.328 210 89 nw 0 0 0 0 55776 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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cap "inv1_q" "inv2_q" 221.335
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cap "WWL" "inv2_q" 79.058
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cap "WBL" "RBL0" 44.376
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cap "GND" "RWL0" 41.2944
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cap "w_210_89#" "RWL1" 0.971508
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cap "GND" "a_672_110#" 8.401
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cap "WBL" "WBLb" 2.93523
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cap "w_210_89#" "WBLb" 0.225462
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cap "WBL" "inv2_q" 46.3334
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cap "RBL1" "RWL1" 26.7591
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cap "w_210_89#" "inv2_q" 8.19793
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cap "WWL" "inv1_q" 127.945
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cap "WBLb" "RBL1" 44.376
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cap "RBL1" "inv2_q" 4.29366
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cap "GND" "RBL0" 62.0595
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cap "GND" "RWL1" 38.7343
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cap "RBL0" "RWL0" 25.2366
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cap "WBL" "inv1_q" 2.75156
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cap "WBL" "WWL" 13.6507
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cap "w_210_89#" "inv1_q" 10.2724
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cap "w_210_89#" "WWL" 5.18244
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cap "VDD" "WBLb" 3.5875
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cap "GND" "a_672_322#" 7.50024
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cap "RWL0" "RWL1" 26.5072
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cap "VDD" "inv2_q" 66.914
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cap "GND" "WBLb" 35.875
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cap "GND" "inv2_q" 174.281
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cap "a_672_110#" "RWL1" 2.86675
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cap "RWL0" "a_672_322#" 2.3207
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cap "RWL0" "inv2_q" 0.89096
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cap "a_672_110#" "inv2_q" 1.35302
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cap "VDD" "inv1_q" 90.953
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cap "WWL" "VDD" 14.2876
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cap "GND" "WWL" 6.61657
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cap "GND" "inv1_q" 70.5352
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cap "RBL0" "a_672_322#" 7.39242
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cap "RWL0" "inv1_q" 11.9459
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cap "WWL" "RWL0" 20.1387
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cap "RBL0" "inv2_q" 0.0710157
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cap "a_672_110#" "inv1_q" 1.58011
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cap "WWL" "a_672_110#" 1.62773
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cap "WBLb" "RWL1" 0.479925
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cap "inv2_q" "RWL1" 10.8463
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cap "w_210_89#" "VDD" 9.687
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cap "GND" "WBL" 37.1236
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cap "GND" "w_210_89#" 1.18526
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cap "a_672_322#" "inv2_q" 3.30277
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cap "WBLb" "inv2_q" 3.32737
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cap "WBL" "RWL0" 0.660698
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cap "w_210_89#" "RWL0" 0.777264
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cap "GND" "RBL1" 59.8597
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cap "RBL0" "inv1_q" 4.09569
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cap "WWL" "RBL0" 0.463335
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cap "inv1_q" "RWL1" 1.02291
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cap "WWL" "RWL1" 19.6967
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cap "a_672_110#" "RBL1" 8.401
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cap "WWL" "a_672_322#" 1.01858
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cap "GND" "VDD" 77.736
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cap "WBLb" "inv1_q" 47.0996
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cap "WWL" "WBLb" 8.787
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device msubckt sky130_fd_pr__nfet_01v8 672 80 673 81 l=30 w=126 "VSUBS" "RWL1" 60 0 "RBL1" 126 9576,404 "a_672_110#" 126 5292,210
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device msubckt sky130_fd_pr__nfet_01v8 448 80 449 81 l=30 w=98 "VSUBS" "WWL" 60 0 "WBLb" 98 7840,356 "inv1_q" 98 4116,182
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device msubckt sky130_fd_pr__nfet_01v8 672 194 673 195 l=30 w=126 "VSUBS" "inv2_q" 60 0 "a_672_110#" 126 5292,210 "GND" 126 4284,194
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device msubckt sky130_fd_pr__nfet_01v8 448 194 449 195 l=30 w=98 "VSUBS" "inv2_q" 60 0 "inv1_q" 98 4116,182 "GND" 98 3332,166
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device msubckt sky130_fd_pr__pfet_01v8 252 194 253 195 l=30 w=84 "w_210_89#" "inv2_q" 60 0 "inv1_q" 84 5460,298 "VDD" 84 2856,152
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device msubckt sky130_fd_pr__nfet_01v8 672 292 673 293 l=30 w=126 "VSUBS" "inv1_q" 60 0 "GND" 126 4284,194 "a_672_322#" 126 4662,200
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device msubckt sky130_fd_pr__nfet_01v8 448 292 449 293 l=30 w=98 "VSUBS" "inv1_q" 60 0 "GND" 98 3332,166 "inv2_q" 98 3626,172
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device msubckt sky130_fd_pr__pfet_01v8 252 292 253 293 l=30 w=84 "w_210_89#" "inv1_q" 60 0 "VDD" 84 2856,152 "inv2_q" 84 4956,286
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device msubckt sky130_fd_pr__nfet_01v8 672 396 673 397 l=30 w=126 "VSUBS" "RWL0" 60 0 "a_672_322#" 126 4662,200 "RBL0" 126 9828,408
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device msubckt sky130_fd_pr__nfet_01v8 448 396 449 397 l=30 w=98 "VSUBS" "WWL" 60 0 "inv2_q" 98 3626,172 "WBL" 98 7252,344
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Binary file not shown.
@ -0,0 +1,146 @@
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VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO toysram_bit
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CLASS BLOCK ;
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FOREIGN toysram_bit ;
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ORIGIN 0.000 0.000 ;
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SIZE 4.750 BY 2.500 ;
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PIN WWL
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ANTENNAGATEAREA 0.147000 ;
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PORT
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LAYER li1 ;
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RECT 0.110 1.940 0.450 2.280 ;
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RECT 0.110 0.400 0.450 0.740 ;
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LAYER mcon ;
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RECT 0.195 2.025 0.365 2.195 ;
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RECT 0.195 0.485 0.365 0.655 ;
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LAYER met1 ;
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RECT 0.110 1.940 0.450 2.280 ;
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RECT 0.110 0.400 0.450 0.740 ;
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LAYER via ;
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RECT 0.140 1.970 0.420 2.250 ;
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RECT 0.140 0.430 0.420 0.710 ;
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LAYER met2 ;
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RECT 0.000 1.940 0.560 2.280 ;
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RECT 0.110 0.400 0.450 1.940 ;
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END
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END WWL
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PIN WBL
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ANTENNADIFFAREA 0.181300 ;
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PORT
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LAYER li1 ;
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RECT 2.315 2.160 2.655 2.500 ;
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LAYER mcon ;
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RECT 2.400 2.245 2.570 2.415 ;
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LAYER met1 ;
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RECT 1.960 2.160 2.800 2.500 ;
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END
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END WBL
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PIN GND
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ANTENNADIFFAREA 0.380800 ;
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PORT
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LAYER li1 ;
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RECT 2.315 1.120 2.655 1.460 ;
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RECT 3.505 1.120 3.845 1.460 ;
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LAYER mcon ;
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RECT 2.400 1.205 2.570 1.375 ;
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RECT 3.590 1.205 3.760 1.375 ;
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LAYER met1 ;
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RECT 2.100 1.120 4.750 1.460 ;
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END
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END GND
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PIN VDD
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ANTENNADIFFAREA 0.142800 ;
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PORT
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LAYER li1 ;
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RECT 1.300 1.120 1.640 1.460 ;
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LAYER mcon ;
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RECT 1.385 1.205 1.555 1.375 ;
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LAYER met1 ;
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RECT 1.050 1.120 1.890 1.460 ;
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END
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END VDD
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PIN WBLb
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ANTENNADIFFAREA 0.196000 ;
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PORT
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LAYER li1 ;
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RECT 2.315 0.060 2.655 0.400 ;
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LAYER mcon ;
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RECT 2.400 0.145 2.570 0.315 ;
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LAYER met1 ;
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RECT 1.820 0.060 2.800 0.400 ;
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END
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END WBLb
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PIN RBL0
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ANTENNADIFFAREA 0.245700 ;
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PORT
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LAYER li1 ;
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RECT 3.505 2.160 3.845 2.500 ;
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LAYER mcon ;
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RECT 3.590 2.245 3.760 2.415 ;
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LAYER met1 ;
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RECT 3.220 2.160 4.130 2.500 ;
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END
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END RBL0
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PIN RBL1
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ANTENNADIFFAREA 0.239400 ;
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PORT
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LAYER li1 ;
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RECT 3.505 0.060 3.845 0.400 ;
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LAYER mcon ;
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RECT 3.590 0.145 3.760 0.315 ;
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LAYER met1 ;
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RECT 3.220 0.060 4.130 0.400 ;
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END
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END RBL1
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PIN RWL0
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ANTENNAGATEAREA 0.094500 ;
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PORT
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LAYER li1 ;
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RECT 4.410 1.895 4.750 2.235 ;
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LAYER mcon ;
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RECT 4.495 1.980 4.665 2.150 ;
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LAYER met1 ;
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RECT 4.410 1.895 4.750 2.235 ;
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LAYER via ;
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RECT 4.440 1.925 4.720 2.205 ;
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LAYER met2 ;
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RECT 4.410 1.895 4.750 2.235 ;
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END
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END RWL0
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PIN RWL1
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ANTENNAGATEAREA 0.094500 ;
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PORT
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LAYER li1 ;
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RECT 4.410 0.315 4.750 0.655 ;
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LAYER mcon ;
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RECT 4.495 0.400 4.665 0.570 ;
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LAYER met1 ;
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RECT 4.410 0.315 4.750 0.655 ;
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LAYER via ;
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RECT 4.440 0.345 4.720 0.625 ;
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LAYER met2 ;
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RECT 4.410 0.315 4.750 0.655 ;
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END
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END RWL1
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OBS
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LAYER pwell ;
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RECT 3.230 2.630 4.120 2.650 ;
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LAYER nwell ;
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RECT 1.050 0.445 1.890 2.105 ;
|
||||
LAYER pwell ;
|
||||
RECT 2.110 -0.110 4.120 2.630 ;
|
||||
RECT 2.110 -0.130 2.860 -0.110 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.460 1.375 0.800 1.715 ;
|
||||
RECT 0.980 1.680 3.080 1.850 ;
|
||||
RECT 0.630 0.890 0.800 1.375 ;
|
||||
RECT 2.910 1.225 3.080 1.680 ;
|
||||
RECT 0.630 0.720 2.730 0.890 ;
|
||||
RECT 2.910 0.885 3.250 1.225 ;
|
||||
END
|
||||
END toysram_bit
|
||||
END LIBRARY
|
||||
|
||||
@ -0,0 +1,11 @@
|
||||
| units: 500000 tech: sky130A format: MIT
|
||||
x RWL0 a_672_322# RBL0 VSUBS s=4662,200 d=9828,408 l=30 w=126 x=672 y=396 sky130_fd_pr__nfet_01v8
|
||||
x inv2_q inv1_q GND VSUBS s=4116,182 d=3332,166 l=30 w=98 x=448 y=194 sky130_fd_pr__nfet_01v8
|
||||
x inv1_q GND inv2_q VSUBS s=3332,166 d=3626,172 l=30 w=98 x=448 y=292 sky130_fd_pr__nfet_01v8
|
||||
x WWL inv2_q WBL VSUBS s=3626,172 d=7252,344 l=30 w=98 x=448 y=396 sky130_fd_pr__nfet_01v8
|
||||
x inv1_q VDD inv2_q w_210_89# s=2856,152 d=4956,286 l=30 w=84 x=252 y=292 sky130_fd_pr__pfet_01v8
|
||||
x inv2_q inv1_q VDD w_210_89# s=5460,298 d=2856,152 l=30 w=84 x=252 y=194 sky130_fd_pr__pfet_01v8
|
||||
x WWL WBLb inv1_q VSUBS s=7840,356 d=4116,182 l=30 w=98 x=448 y=80 sky130_fd_pr__nfet_01v8
|
||||
x RWL1 RBL1 a_672_110# VSUBS s=9576,404 d=5292,210 l=30 w=126 x=672 y=80 sky130_fd_pr__nfet_01v8
|
||||
x inv2_q a_672_110# GND VSUBS s=5292,210 d=4284,194 l=30 w=126 x=672 y=194 sky130_fd_pr__nfet_01v8
|
||||
x inv1_q GND a_672_322# VSUBS s=4284,194 d=4662,200 l=30 w=126 x=672 y=292 sky130_fd_pr__nfet_01v8
|
||||
@ -0,0 +1,14 @@
|
||||
* NGSPICE file created from toysram_bit.ext - technology: sky130A
|
||||
|
||||
.subckt toysram_bit WWL WBL inv2_q GND VDD inv1_q WBLb RBL0 RBL1 RWL0 RWL1
|
||||
X0 RBL0 RWL0 a_672_322# VSUBS sky130_fd_pr__nfet_01v8 ad=0.246 pd=2.04 as=0.117 ps=1 w=0.63 l=0.15
|
||||
X1 GND inv2_q inv1_q VSUBS sky130_fd_pr__nfet_01v8 ad=0.0833 pd=0.83 as=0.103 ps=0.91 w=0.49 l=0.15
|
||||
X2 inv2_q inv1_q GND VSUBS sky130_fd_pr__nfet_01v8 ad=0.0906 pd=0.86 as=0.0833 ps=0.83 w=0.49 l=0.15
|
||||
X3 WBL WWL inv2_q VSUBS sky130_fd_pr__nfet_01v8 ad=0.181 pd=1.72 as=0.0906 ps=0.86 w=0.49 l=0.15
|
||||
X4 inv2_q inv1_q VDD w_210_89# sky130_fd_pr__pfet_01v8 ad=0.124 pd=1.43 as=0.0714 ps=0.76 w=0.42 l=0.15
|
||||
X5 VDD inv2_q inv1_q w_210_89# sky130_fd_pr__pfet_01v8 ad=0.0714 pd=0.76 as=0.137 ps=1.49 w=0.42 l=0.15
|
||||
X6 inv1_q WWL WBLb VSUBS sky130_fd_pr__nfet_01v8 ad=0.103 pd=0.91 as=0.196 ps=1.78 w=0.49 l=0.15
|
||||
X7 a_672_110# RWL1 RBL1 VSUBS sky130_fd_pr__nfet_01v8 ad=0.132 pd=1.05 as=0.239 ps=2.02 w=0.63 l=0.15
|
||||
X8 GND inv2_q a_672_110# VSUBS sky130_fd_pr__nfet_01v8 ad=0.107 pd=0.97 as=0.132 ps=1.05 w=0.63 l=0.15
|
||||
X9 a_672_322# inv1_q GND VSUBS sky130_fd_pr__nfet_01v8 ad=0.117 pd=1 as=0.107 ps=0.97 w=0.63 l=0.15
|
||||
.ends
|
||||
Loading…
Reference in New Issue