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23 lines
428 B
Markdown
23 lines
428 B
Markdown
2 years ago
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## Logical Array Wrapper
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* verilog is in rtl/src/array
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* parameter determines sim vs tech during rtl compile
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## Physical Array
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* custom cell(s) to be designed
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* custom/
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## Test Site
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* verilog is in rtl/src/site
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* supporting logic for test and debug through available Caravel connections
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## Verification
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* rtl/sim/coco
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## Caravel
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* to be incorporated into https://github.com/efabless/caravel flow as a user project area
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