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43 lines
816 B
Plaintext
43 lines
816 B
Plaintext
3 years ago
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## Cells needed for the Skywater test site
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We need to produce the necessary
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* Schematic
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* Layout
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* Logic and timing models for
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### Low level cells
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1) 10T SRAM
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a. WWL, RWL0, , RWL1
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b. (WBL WBL_B), RBL0, RBL1
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2) Local eval (NAND2 with 2 precharged inputs)
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a. PC_Left, PC_Right, In_Left, In_Right -> Q (output)
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3) LSDL state-holding latch (Latch with 2 dynamic inputs forming an 'Or')
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a. In_Left, In_Right, CLK -> Q (output)
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### Mid level cell
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Partially decode 2R1W 64Rx24 bit array). (Includes early/late output latch)
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Inputs:
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1) Clock*A0,Clock*~A0
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2) ~A1*~A2,~A1,*~A2, A1*~A2,A1*~A2,
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3) A3 ,~A3
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4) ~A4*~A5,~A4,*~A5, A14*~A5,A4*~A5,
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5) DataIn0..DI23
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6) Early and late Clock for LSDL state holding latch.
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Outputs:
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1) DataOut00..DO023
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2) DO10..DO123
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3) DO20..DO223
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4) DO30..DO323
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