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1 year ago
## Logical Array Wrapper
* verilog is in rtl/src/array
* parameter determines sim vs tech during rtl compile
## Physical Array
* custom cell(s) to be designed
* custom/
## Test Site
* verilog is in rtl/src/site
* supporting logic for test and debug through available Caravel connections
## Verification
* rtl/sim/coco
## Caravel
* to be incorporated into flow as a user project area