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Jean-François Nguyen e30ea40a8b check.insn: ignore upper SPR 32-bits when pfv.gpr_width=32. 11 months ago
cores/microwatt pfv: add configurable memory alignment constraints. 11 months ago
power_fv check.insn: ignore upper SPR 32-bits when pfv.gpr_width=32. 11 months ago
.gitignore initial push with a gitignore file 1 year ago
LICENSE.txt Add license. 1 year ago README: fix styling, update microwatt URL. 1 year ago
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POWER-FV Assertion-based formal verification library for OpenPOWER processors


This project is currently in an experimental state. In particular:

  • it has only been tried on the Microwatt CPU
  • it assumes an in-order scalar core
  • its instruction coverage is limited to the Scalar Fixed-point Compliancy Subset
  • the correctness of its own specifications hasn't yet been verified


POWER-FV is a formal verification library that can be used to check the compliance of a processor with the OpenPOWER ISA. It provides an interface to trace the execution of a processor, which is monitored by a testbench and compared against a given specification.

Testbenches and behavioral models are implemented in Python using Amaranth HDL, and SymbiYosys for its formal verification flow. Processor cores may use any HDL supported by Yosys.

POWER-FV's design is heavily inspired by the riscv-formal framework, developed by Claire Wolf (YosysHQ).


If VHDL support is needed:

The OSS CAD Suite can provide pre-built binaries of these tools.


pip3 install poetry --user
poetry install


See the cores folder for usage examples.