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10 Commits (05965592f963101247aaa688122d904331cc8f08)

Author SHA1 Message Date
Jean-François Nguyen 05965592f9 checks.insn._addsub: fix incorrect ADDEX updates to OV/OV32. 3 years ago
Jean-François Nguyen f06c8000b0 checks.insn: add checks for add/subtract instructions. 3 years ago
Jean-François Nguyen 8cf56ab5dc checks.insn: add checks for MTSPR and MFSPR instructions. 3 years ago
Jean-François Nguyen 692e8ec7c4 checks.insn: add checks for compare instructions. 3 years ago
Jean-François Nguyen a413025fcb Update SPR interface and split consistency check. 
* Use bitmasks to describe SPR accesses at the field granularity.

* Use separate checks for each SPR, instead of covering them all at
  once. Users may run them in the same batch, and know which SPR passes
  or fails its check.
 3 years ago
Jean-François Nguyen 2ffff6196b checks.insn: add check for MCRF instruction. 4 years ago
Jean-François Nguyen 4c16035a70 checks.insn._cr: fix order of spec_cr_w_data bits. 4 years ago
Jean-François Nguyen fee59d2257 checks.insn: add checks for CR logical instructions. 4 years ago
Jean-François Nguyen bc06e67fe8 checks.insn._branch: add missing PowerFVCheck name. 4 years ago
Jean-François Nguyen 9ea58a47a9 Refactor to facilitate integration with CLIs and config files. 
* Checks are now split in two modules: checks.cons for consistency
  checks, checks.insn for instructions.

* Checks are derived from PowerFVCheck and have a shorthand (e.g.
  "insn_b"). PowerFVCheck holds a mapping between its subclasses and
  their shorthands.

* Instruction checks definitions have been simplified to one-liners,
  and grouped into a single file.

* A Trigger class has been added to define testbench triggers.
 4 years ago