checks.insn._cr: fix order of spec_cr_w_data bits.

2 years ago · 4c16035a70
parent 010c383ed7
commit 4c16035a70
1 changed files with 1 additions and 1 deletions
--- a/power_fv/checks/insn/_cr.py
+++ b/power_fv/checks/insn/_cr.py
@ -87,7 +87,7 @@ class CRSpec(Elaboratable):
                spec_cr_r_stb[::-1].bit_select(spec_insn.ba[2:], width=1).eq(1),
                spec_cr_r_stb[::-1].bit_select(spec_insn.bb[2:], width=1).eq(1),
                spec_cr_w_stb[::-1].bit_select(spec_insn.bt[2:], width=1).eq(1),
-                spec_cr_w_data.eq(Repl(spec_bt_w_field, 8))
+                spec_cr_w_data[::-1].eq(Repl(spec_bt_w_field, 8))
            ]
        else:
            assert False