build.plat: sby mode override; cosmetic fixes.

power_fv/build/plat.py

@@ -1,6 +1,8 @@
 from amaranth import *
 from amaranth.build import *
 
+from .. import tb
+
 
 __all__ = ["SymbiYosysPlatform"]
 
@@ -11,7 +13,7 @@ class SymbiYosysPlatform(TemplatedPlatform):
         * ``yosys``
         * ``sby``
 
-    Required tools for VHDL support:
+    Required tools for VHDL support (experimental):
         * ``ghdl``
         * ``ghdl-yosys-plugin``
 
@@ -45,11 +47,11 @@ class SymbiYosysPlatform(TemplatedPlatform):
         "{{name}}.sby": r"""
             # {{autogenerated}}
             [options]
-            mode bmc
+            mode {{get_override("mode")}}
             expect pass,fail
             append 0
-            depth {{get_override("sby_depth")}}
+            depth {{get_override("depth")}}
-            skip {{get_override("sby_skip")}}
+            skip {{get_override("skip")}}
 
             [engines]
             smtbmc
@@ -72,12 +74,11 @@ class SymbiYosysPlatform(TemplatedPlatform):
                 read_verilog {{get_override("read_verilog_opts")|default("-sv")}} {{file}}
             {% endfor %}
             {% if platform.iter_files(".vhdl")|first is defined -%}
-                ghdl {{get_override("ghdl_opts")|options}} {{platform.iter_files(".vhdl")|join(" ")}} -e {{get_override("ghdl_top")|default("top")}}
+                ghdl {{get_override("ghdl_opts")|options}} {{platform.iter_files(".vhdl")|join(" ")}} -e {{get_override("ghdl_top")|default("toplevel")}}
             {% endif %}
             read_ilang {{name}}.il
             delete w:$verilog_initial_trigger
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
-            write_ilang debug.il
             prep {{get_override("prep_opts")|default("-flatten -nordff")}} -top {{name}}
             chformal {{get_override("chformal_opts")|default("-early")}}
         """,
@@ -85,8 +86,8 @@ class SymbiYosysPlatform(TemplatedPlatform):
     command_templates = [
         r"""
             {{invoke_tool("sby")}}
-                --yosys={{invoke_tool("yosys")}}
                 {{get_override("sby_opts")|default("-f")}}
+                --yosys={{invoke_tool("yosys")}}
                 {{name}}.sby
         """,
     ]
@@ -111,5 +112,12 @@ class SymbiYosysPlatform(TemplatedPlatform):
             ]
             return m
 
-    def build(self, elaboratable, *, sby_depth, sby_skip, **kwargs):
+    def build(self, tb, **kwargs):
-        return super().build(elaboratable, sby_depth=sby_depth, sby_skip=sby_skip, **kwargs)
+        if not isinstance(tb, tb.Testbench):
+            raise TypeError("Testbench must be an instance of power_fv.tb.Testbench")
+
+        mode  = tb.check.mode
+        skip  = tb.t_post
+        depth = skip + 1
+
+        return super().build(tb, mode=mode, depth=depth, skip=skip, **kwargs)