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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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use work.powerfv_types.all;
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entity toplevel is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Alternate reset (0xffff0000) for use by DRAM init fw
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alt_reset : in std_ulogic;
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-- Wishbone interface
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wishbone_insn_in : in wishbone_slave_out;
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wishbone_insn_out : out wishbone_master_out;
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wishbone_data_in : in wishbone_slave_out;
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wishbone_data_out : out wishbone_master_out;
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wb_snoop_in : in wishbone_master_out;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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ext_irq : in std_ulogic;
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terminated_out : out std_logic;
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pfv_stb : out std_ulogic;
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pfv_insn : out std_ulogic_vector(63 downto 0);
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pfv_order : out std_ulogic_vector(63 downto 0);
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pfv_intr : out std_ulogic;
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pfv_cia : out std_ulogic_vector(63 downto 0);
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pfv_nia : out std_ulogic_vector(63 downto 0);
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pfv_ra_index : out std_ulogic_vector( 4 downto 0);
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pfv_ra_r_stb : out std_ulogic;
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pfv_ra_r_data : out std_ulogic_vector(63 downto 0);
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pfv_ra_w_stb : out std_ulogic;
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pfv_ra_w_data : out std_ulogic_vector(63 downto 0);
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pfv_rb_index : out std_ulogic_vector( 4 downto 0);
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pfv_rb_r_stb : out std_ulogic;
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pfv_rb_r_data : out std_ulogic_vector(63 downto 0);
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pfv_rs_index : out std_ulogic_vector( 4 downto 0);
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pfv_rs_r_stb : out std_ulogic;
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pfv_rs_r_data : out std_ulogic_vector(63 downto 0);
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pfv_rt_index : out std_ulogic_vector( 4 downto 0);
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pfv_rt_r_stb : out std_ulogic;
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pfv_rt_r_data : out std_ulogic_vector(63 downto 0);
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pfv_rt_w_stb : out std_ulogic;
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pfv_rt_w_data : out std_ulogic_vector(63 downto 0);
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pfv_cr_r_stb : out std_ulogic_vector( 7 downto 0);
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pfv_cr_r_data : out std_ulogic_vector(31 downto 0);
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pfv_cr_w_stb : out std_ulogic_vector( 7 downto 0);
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pfv_cr_w_data : out std_ulogic_vector(31 downto 0);
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pfv_lr_r_stb : out std_ulogic;
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pfv_lr_r_data : out std_ulogic_vector(63 downto 0);
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pfv_lr_w_stb : out std_ulogic;
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pfv_lr_w_data : out std_ulogic_vector(63 downto 0);
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pfv_ctr_r_stb : out std_ulogic;
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pfv_ctr_r_data : out std_ulogic_vector(63 downto 0);
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pfv_ctr_w_stb : out std_ulogic;
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pfv_ctr_w_data : out std_ulogic_vector(63 downto 0);
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pfv_xer_r_stb : out std_ulogic;
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pfv_xer_r_data : out std_ulogic_vector(63 downto 0);
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pfv_xer_w_stb : out std_ulogic;
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pfv_xer_w_data : out std_ulogic_vector(63 downto 0);
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pfv_tar_r_stb : out std_ulogic;
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pfv_tar_r_data : out std_ulogic_vector(63 downto 0);
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pfv_tar_w_stb : out std_ulogic;
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pfv_tar_w_data : out std_ulogic_vector(63 downto 0)
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);
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end entity toplevel;
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architecture behave of toplevel is
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signal pfv : pfv_t;
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begin
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core: entity work.core
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generic map (
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SIM => false,
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DISABLE_FLATTEN => false,
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EX1_BYPASS => true,
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HAS_FPU => false,
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HAS_BTC => true,
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HAS_SHORT_MULT => false,
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HAS_POWERFV => true,
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LOG_LENGTH => 0,
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ICACHE_NUM_LINES => 2,
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ICACHE_NUM_WAYS => 1,
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ICACHE_TLB_SIZE => 1,
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DCACHE_NUM_LINES => 2,
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DCACHE_NUM_WAYS => 1,
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DCACHE_TLB_SET_SIZE => 1,
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DCACHE_TLB_NUM_WAYS => 1
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)
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port map (
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clk => clk,
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rst => rst,
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alt_reset => alt_reset,
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wishbone_insn_in => wishbone_insn_in,
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wishbone_insn_out => wishbone_insn_out,
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wishbone_data_in => wishbone_data_in,
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wishbone_data_out => wishbone_data_out,
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wb_snoop_in => wb_snoop_in,
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dmi_addr => dmi_addr,
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dmi_din => dmi_din,
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dmi_dout => dmi_dout,
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dmi_req => dmi_req,
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dmi_wr => dmi_wr,
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dmi_ack => dmi_ack,
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ext_irq => ext_irq,
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terminated_out => terminated_out,
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pfv_out => pfv
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);
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pfv_stb <= pfv.stb;
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pfv_insn <= pfv.insn;
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pfv_order <= pfv.order;
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pfv_intr <= pfv.intr;
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pfv_cia <= pfv.cia;
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pfv_nia <= pfv.nia;
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pfv_ra_index <= pfv.ra.index;
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pfv_ra_r_stb <= pfv.ra.r_stb;
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pfv_ra_r_data <= pfv.ra.r_data;
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pfv_ra_w_stb <= pfv.ra.w_stb;
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pfv_ra_w_data <= pfv.ra.w_data;
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pfv_rb_index <= pfv.rb.index;
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pfv_rb_r_stb <= pfv.rb.r_stb;
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pfv_rb_r_data <= pfv.rb.r_data;
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pfv_rs_index <= pfv.rs.index;
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pfv_rs_r_stb <= pfv.rs.r_stb;
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pfv_rs_r_data <= pfv.rs.r_data;
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pfv_rt_index <= pfv.rt.index;
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pfv_rt_r_stb <= pfv.rt.r_stb;
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pfv_rt_r_data <= pfv.rt.r_data;
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pfv_rt_w_stb <= pfv.rt.w_stb;
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pfv_rt_w_data <= pfv.rt.w_data;
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pfv_cr_r_stb <= pfv.cr.r_stb;
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pfv_cr_r_data <= pfv.cr.r_data;
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pfv_cr_w_stb <= pfv.cr.w_stb;
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pfv_cr_w_data <= pfv.cr.w_data;
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pfv_lr_r_stb <= pfv.lr.r_stb;
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pfv_lr_r_data <= pfv.lr.r_data;
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pfv_lr_w_stb <= pfv.lr.w_stb;
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pfv_lr_w_data <= pfv.lr.w_data;
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pfv_ctr_r_stb <= pfv.ctr.r_stb;
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pfv_ctr_r_data <= pfv.ctr.r_data;
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pfv_ctr_w_stb <= pfv.ctr.w_stb;
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pfv_ctr_w_data <= pfv.ctr.w_data;
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pfv_xer_r_stb <= pfv.xer.r_stb;
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pfv_xer_r_data <= pfv.xer.r_data;
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pfv_xer_w_stb <= pfv.xer.w_stb;
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pfv_xer_w_data <= pfv.xer.w_data;
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pfv_tar_r_stb <= pfv.tar.r_stb;
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pfv_tar_r_data <= pfv.tar.r_data;
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pfv_tar_w_stb <= pfv.tar.w_stb;
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pfv_tar_w_data <= pfv.tar.w_data;
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end architecture behave;
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