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cores/microwatt: add support for CRCheck.

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Jean-François Nguyen 4 years ago
parent e7e9bb08f0
commit ca66e3a45e
3 changed files with 109 additions and 1 deletions
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40
cores/microwatt/_wrapper.py
Unescape Escape View File

@ -120,6 +120,46 @@ class MicrowattWrapper(Elaboratable):
("o", "pfv_rt_r_data", self.pfv.rt.r_data),
("o", "pfv_rt_w_stb", self.pfv.rt.w_stb),
("o", "pfv_rt_w_data", self.pfv.rt.w_data),

("o", "pfv_cr0_r_stb", self.pfv.cr0.r_stb),
("o", "pfv_cr0_r_data", self.pfv.cr0.r_data),
("o", "pfv_cr0_w_stb", self.pfv.cr0.w_stb),
("o", "pfv_cr0_w_data", self.pfv.cr0.w_data),

("o", "pfv_cr1_r_stb", self.pfv.cr1.r_stb),
("o", "pfv_cr1_r_data", self.pfv.cr1.r_data),
("o", "pfv_cr1_w_stb", self.pfv.cr1.w_stb),
("o", "pfv_cr1_w_data", self.pfv.cr1.w_data),

("o", "pfv_cr2_r_stb", self.pfv.cr2.r_stb),
("o", "pfv_cr2_r_data", self.pfv.cr2.r_data),
("o", "pfv_cr2_w_stb", self.pfv.cr2.w_stb),
("o", "pfv_cr2_w_data", self.pfv.cr2.w_data),

("o", "pfv_cr3_r_stb", self.pfv.cr3.r_stb),
("o", "pfv_cr3_r_data", self.pfv.cr3.r_data),
("o", "pfv_cr3_w_stb", self.pfv.cr3.w_stb),
("o", "pfv_cr3_w_data", self.pfv.cr3.w_data),

("o", "pfv_cr4_r_stb", self.pfv.cr4.r_stb),
("o", "pfv_cr4_r_data", self.pfv.cr4.r_data),
("o", "pfv_cr4_w_stb", self.pfv.cr4.w_stb),
("o", "pfv_cr4_w_data", self.pfv.cr4.w_data),

("o", "pfv_cr5_r_stb", self.pfv.cr5.r_stb),
("o", "pfv_cr5_r_data", self.pfv.cr5.r_data),
("o", "pfv_cr5_w_stb", self.pfv.cr5.w_stb),
("o", "pfv_cr5_w_data", self.pfv.cr5.w_data),

("o", "pfv_cr6_r_stb", self.pfv.cr6.r_stb),
("o", "pfv_cr6_r_data", self.pfv.cr6.r_data),
("o", "pfv_cr6_w_stb", self.pfv.cr6.w_stb),
("o", "pfv_cr6_w_data", self.pfv.cr6.w_data),

("o", "pfv_cr7_r_stb", self.pfv.cr7.r_stb),
("o", "pfv_cr7_r_data", self.pfv.cr7.r_data),
("o", "pfv_cr7_w_stb", self.pfv.cr7.w_stb),
("o", "pfv_cr7_w_data", self.pfv.cr7.w_data),
)

with m.If(Initial()):

66
cores/microwatt/microwatt_top.vhdl
Unescape Escape View File

@ -58,6 +58,39 @@ entity toplevel is
pfv_rt_r_data : out std_ulogic_vector(63 downto 0);
pfv_rt_w_stb : out std_ulogic;
pfv_rt_w_data : out std_ulogic_vector(63 downto 0);

pfv_cr0_r_stb : out std_ulogic;
pfv_cr0_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr0_w_stb : out std_ulogic;
pfv_cr0_w_data : out std_ulogic_vector(3 downto 0);
pfv_cr1_r_stb : out std_ulogic;
pfv_cr1_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr1_w_stb : out std_ulogic;
pfv_cr1_w_data : out std_ulogic_vector(3 downto 0);
pfv_cr2_r_stb : out std_ulogic;
pfv_cr2_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr2_w_stb : out std_ulogic;
pfv_cr2_w_data : out std_ulogic_vector(3 downto 0);
pfv_cr3_r_stb : out std_ulogic;
pfv_cr3_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr3_w_stb : out std_ulogic;
pfv_cr3_w_data : out std_ulogic_vector(3 downto 0);
pfv_cr4_r_stb : out std_ulogic;
pfv_cr4_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr4_w_stb : out std_ulogic;
pfv_cr4_w_data : out std_ulogic_vector(3 downto 0);
pfv_cr5_r_stb : out std_ulogic;
pfv_cr5_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr5_w_stb : out std_ulogic;
pfv_cr5_w_data : out std_ulogic_vector(3 downto 0);
pfv_cr6_r_stb : out std_ulogic;
pfv_cr6_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr6_w_stb : out std_ulogic;
pfv_cr6_w_data : out std_ulogic_vector(3 downto 0);
pfv_cr7_r_stb : out std_ulogic;
pfv_cr7_r_data : out std_ulogic_vector(3 downto 0);
pfv_cr7_w_stb : out std_ulogic;
pfv_cr7_w_data : out std_ulogic_vector(3 downto 0)
);
end entity toplevel;

@ -126,4 +159,37 @@ begin
pfv_rt_w_stb <= pfv.rt.w_stb;
pfv_rt_w_data <= pfv.rt.w_data;

pfv_cr0_r_stb <= pfv.cr(0).r_stb;
pfv_cr0_r_data <= pfv.cr(0).r_data;
pfv_cr0_w_stb <= pfv.cr(0).w_stb;
pfv_cr0_w_data <= pfv.cr(0).w_data;
pfv_cr1_r_stb <= pfv.cr(1).r_stb;
pfv_cr1_r_data <= pfv.cr(1).r_data;
pfv_cr1_w_stb <= pfv.cr(1).w_stb;
pfv_cr1_w_data <= pfv.cr(1).w_data;
pfv_cr2_r_stb <= pfv.cr(2).r_stb;
pfv_cr2_r_data <= pfv.cr(2).r_data;
pfv_cr2_w_stb <= pfv.cr(2).w_stb;
pfv_cr2_w_data <= pfv.cr(2).w_data;
pfv_cr3_r_stb <= pfv.cr(3).r_stb;
pfv_cr3_r_data <= pfv.cr(3).r_data;
pfv_cr3_w_stb <= pfv.cr(3).w_stb;
pfv_cr3_w_data <= pfv.cr(3).w_data;
pfv_cr4_r_stb <= pfv.cr(4).r_stb;
pfv_cr4_r_data <= pfv.cr(4).r_data;
pfv_cr4_w_stb <= pfv.cr(4).w_stb;
pfv_cr4_w_data <= pfv.cr(4).w_data;
pfv_cr5_r_stb <= pfv.cr(5).r_stb;
pfv_cr5_r_data <= pfv.cr(5).r_data;
pfv_cr5_w_stb <= pfv.cr(5).w_stb;
pfv_cr5_w_data <= pfv.cr(5).w_data;
pfv_cr6_r_stb <= pfv.cr(6).r_stb;
pfv_cr6_r_data <= pfv.cr(6).r_data;
pfv_cr6_w_stb <= pfv.cr(6).w_stb;
pfv_cr6_w_data <= pfv.cr(6).w_data;
pfv_cr7_r_stb <= pfv.cr(7).r_stb;
pfv_cr7_r_data <= pfv.cr(7).r_data;
pfv_cr7_w_stb <= pfv.cr(7).w_stb;
pfv_cr7_w_data <= pfv.cr(7).w_data;

end architecture behave;

4
cores/microwatt/run.py
Unescape Escape View File

@ -14,7 +14,7 @@ from _wrapper import MicrowattWrapper

if __name__ == "__main__":
parser = argparse.ArgumentParser()
parser.add_argument("check", help="check", type=str, choices=("unique", "ia_fwd", "gpr"))
parser.add_argument("check", help="check", type=str, choices=("unique", "ia_fwd", "gpr", "cr"))
parser.add_argument("--mode", help="mode", type=str, choices=("cover", "bmc"), default="bmc")
parser.add_argument("--pre", help="pre-condition step, in clock cycles (default: 15)", type=int, default=15)
parser.add_argument("--post", help="post-condition step, in clock cycles (default: 15)", type=int, default=15)
@ -28,6 +28,8 @@ if __name__ == "__main__":
check = IAForwardCheck() if args.mode == "bmc" else IAForwardCover()
if args.check == "gpr":
check = GPRCheck()
if args.check == "cr":
check = CRCheck()

cpu = MicrowattWrapper()
testbench = Testbench(check, cpu, t_pre=args.pre, t_post=args.post)

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