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Paul Mackerras
45cd8f4fc3
This extends the register file so it can hold FPR values, and implements the FP loads and stores that do not require conversion between single and double precision. We now have the FP, FE0 and FE1 bits in MSR. FP loads and stores cause a FP unavailable interrupt if MSR[FP] = 0. The FPU facilities are optional and their presence is controlled by the HAS_FPU generic passed down from the top-level board file. It defaults to true for all except the A7-35 boards. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
4 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | 4 years ago | |
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | 4 years ago | |
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | 4 years ago | |
| fpga-random.xdc | 4 years ago | |
| genesys2.xdc | 4 years ago | |
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | 4 years ago | |
| top-arty.vhdl | 4 years ago | |
| top-generic.vhdl | 4 years ago | |
| top-genesys2.vhdl | 4 years ago | |
| top-nexys-video.vhdl | 4 years ago | |